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authorKirill A. Shutemov <kirill.shutemov@linux.intel.com>2021-12-22 19:33:51 +0300
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2021-12-27 19:01:28 +0300
commit1d4e0b3abb168b2ee1eca99c527cffa1b80b6161 (patch)
tree3630ebea60ec4d2ba61b1ee68e7c0291bf192cd6 /drivers/acpi/acpica/hwesleep.c
parent0acf24ad7e10f547809faefb8069f8f5482eb4d9 (diff)
downloadlinux-1d4e0b3abb168b2ee1eca99c527cffa1b80b6161.tar.xz
ACPICA: Hardware: Do not flush CPU cache when entering S4 and S5
ACPICA commit 3dd7e1f3996456ef81bfe14cba29860e8d42949e According to ACPI 6.4, Section 16.2, the CPU cache flushing is required on entering to S1, S2, and S3, but the ACPICA code flushes the CPU cache regardless of the sleep state. Blind cache flush on entering S5 causes problems for TDX. Flushing happens with WBINVD that is not supported in the TDX environment. TDX only supports S5 and adjusting ACPICA code to conform to the spec more strictly fixes the issue. Link: https://github.com/acpica/acpica/commit/3dd7e1f3 Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> [ rjw: Subject and changelog edits ] Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'drivers/acpi/acpica/hwesleep.c')
-rw-r--r--drivers/acpi/acpica/hwesleep.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/acpi/acpica/hwesleep.c b/drivers/acpi/acpica/hwesleep.c
index 808fdf54aeeb..7ee2939c08cd 100644
--- a/drivers/acpi/acpica/hwesleep.c
+++ b/drivers/acpi/acpica/hwesleep.c
@@ -104,7 +104,9 @@ acpi_status acpi_hw_extended_sleep(u8 sleep_state)
/* Flush caches, as per ACPI specification */
- ACPI_FLUSH_CPU_CACHE();
+ if (sleep_state < ACPI_STATE_S4) {
+ ACPI_FLUSH_CPU_CACHE();
+ }
status = acpi_os_enter_sleep(sleep_state, sleep_control, 0);
if (status == AE_CTRL_TERMINATE) {