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authorPeng Fan <peng.fan@nxp.com>2020-03-19 10:49:52 +0300
committerJassi Brar <jaswinder.singh@linaro.org>2020-03-20 07:04:32 +0300
commit0a67003b1985c79811160af1b01aca07cd5fbc53 (patch)
treefbff84d616303f7cd358ff84e2893a75f22c0fb7 /crypto
parent63b383575c388fe16aa52de04b95c5791d53c8ba (diff)
downloadlinux-0a67003b1985c79811160af1b01aca07cd5fbc53.tar.xz
mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A cores from hardware design, and could not be reused for other purpose. Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples", Passing short messages: Transmit register(s) can be used to pass short messages from one to four words in length. For example, when a four-word message is desired, only one of the registers needs to have its corresponding interrupt enable bit set at the receiver side; the message’s first three words are written to the registers whose interrupt is masked, and the fourth word is written to the other register (which triggers an interrupt at the receiver side). i.MX8/8X SCU firmware IPC is an implementation of passing short messages. But current imx-mailbox driver only support one word message, i.MX8/8X linux side firmware has to request four TX and four RX to support IPC to SCU firmware. This is low efficent and more interrupts triggered compared with one TX and one RX. To make SCU MU work, - parse the size of msg. - Only enable TR0/RR0 interrupt for transmit/receive message. - For TX/RX, only support one TX channel and one RX channel - For RX, support receive msg larger than 4 u32 words. - Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB. Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Diffstat (limited to 'crypto')
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