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| author | Boris Brezillon <boris.brezillon@collabora.com> | 2021-06-30 09:27:37 +0300 |
|---|---|---|
| committer | Boris Brezillon <boris.brezillon@collabora.com> | 2021-07-01 09:53:25 +0300 |
| commit | 78efe21b6f8e6f4d39fceaf0cc5c534c11f9dd60 (patch) | |
| tree | 52456ca7d9e03737afb1d1d77a29fed2db167c7a /crypto/ecrdsa_defs.h | |
| parent | 1fad1b7ed1ebfcfb5a1d0d21b0c47f7af5f49a6c (diff) | |
| download | linux-78efe21b6f8e6f4d39fceaf0cc5c534c11f9dd60.tar.xz | |
drm/sched: Allow using a dedicated workqueue for the timeout/fault tdr
Mali Midgard/Bifrost GPUs have 3 hardware queues but only a global GPU
reset. This leads to extra complexity when we need to synchronize timeout
works with the reset work. One solution to address that is to have an
ordered workqueue at the driver level that will be used by the different
schedulers to queue their timeout work. Thanks to the serialization
provided by the ordered workqueue we are guaranteed that timeout
handlers are executed sequentially, and can thus easily reset the GPU
from the timeout handler without extra synchronization.
v5:
* Add a new paragraph to the timedout_job() method
v3:
* New patch
v4:
* Actually use the timeout_wq to queue the timeout work
Suggested-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Steven Price <steven.price@arm.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Christian König <christian.koenig@amd.com>
Cc: Qiang Yu <yuq825@gmail.com>
Cc: Emma Anholt <emma@anholt.net>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Christian König" <christian.koenig@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210630062751.2832545-3-boris.brezillon@collabora.com
Diffstat (limited to 'crypto/ecrdsa_defs.h')
0 files changed, 0 insertions, 0 deletions