diff options
| author | Thierry Reding <treding@nvidia.com> | 2019-12-22 16:59:02 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2020-06-23 19:25:42 +0300 |
| commit | aa78032cab9c66a13580e4a564202bec16e6688f (patch) | |
| tree | 4f8f8478b0608b296b6b45e16148b1b60b3f1b5e /arch | |
| parent | a10b9a2075dc800563f16f5697aa0c7409c03dd3 (diff) | |
| download | linux-aa78032cab9c66a13580e4a564202bec16e6688f.tar.xz | |
arm64: tegra: Fix #address-cells/#size-cells for SRAM on Tegra186
The standard mmio-sram bindings require the #address- and #size-cells
properties to be 1.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra186.dtsi | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 58100fb9cd8b..373f575b8678 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1216,20 +1216,20 @@ sysram@30000000 { compatible = "nvidia,tegra186-sysram", "mmio-sram"; reg = <0x0 0x30000000 0x0 0x50000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x30000000 0x50000>; cpu_bpmp_tx: shmem@4e000 { compatible = "nvidia,tegra186-bpmp-shmem"; - reg = <0x0 0x4e000 0x0 0x1000>; + reg = <0x4e000 0x1000>; label = "cpu-bpmp-tx"; pool; }; cpu_bpmp_rx: shmem@4f000 { compatible = "nvidia,tegra186-bpmp-shmem"; - reg = <0x0 0x4f000 0x0 0x1000>; + reg = <0x4f000 0x1000>; label = "cpu-bpmp-rx"; pool; }; |