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authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>2014-11-21 19:00:09 +0300
committerJason Cooper <jason@lakedaemon.net>2014-11-30 19:40:15 +0300
commit77ea46d1331e5b46ff4dd98e7296eb17355cff75 (patch)
tree6f93ffc2c561250f682a1a2ef324e45d59088360 /arch
parent27432825ae19fc26f099156c666cbcc4861e3e54 (diff)
downloadlinux-77ea46d1331e5b46ff4dd98e7296eb17355cff75.tar.xz
ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume
The armada_370_xp_cpu_resume() until now was used only as the function called by the SoC when returning from a deep idle state (as used in cpuidle, or when the CPU is brought offline using CPU hotplug). However, it is now also used when exiting the suspend to RAM state. In this case, it is the bootloader that calls back into this function, with the MMU left enabled by the BootROM. Having the MMU enabled when entering this function confuses the kerrnel because we are not using the kernel page tables at this point, but in other mvebu functions we use the information on whether the MMU is enabled or not to find out whether we should talk to the coherency fabric using a physical address or a virtual address. To fix that, we simply disable the MMU when entering this function, so that the kernel is in an expected situation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1416585613-2113-13-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-mvebu/pmsu_ll.S8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-mvebu/pmsu_ll.S b/arch/arm/mach-mvebu/pmsu_ll.S
index a945756cfb45..ae7e6b06fadc 100644
--- a/arch/arm/mach-mvebu/pmsu_ll.S
+++ b/arch/arm/mach-mvebu/pmsu_ll.S
@@ -18,6 +18,14 @@
*/
ENTRY(armada_370_xp_cpu_resume)
ARM_BE8(setend be ) @ go BE8 if entered LE
+ /*
+ * Disable the MMU that might have been enabled in BootROM if
+ * this code is used in the resume path of a suspend/resume
+ * cycle.
+ */
+ mrc p15, 0, r1, c1, c0, 0
+ bic r1, #1
+ mcr p15, 0, r1, c1, c0, 0
bl ll_add_cpu_to_smp_group
bl ll_enable_coherency
b cpu_resume