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authorTony Luck <tony.luck@intel.com>2024-05-21 19:10:01 +0300
committerDave Hansen <dave.hansen@linux.intel.com>2024-05-28 20:59:02 +0300
commit2cf615a4519b29a3ad283883d7638279ec1e6b44 (patch)
tree458f7dbe0958529f822eeba7eb2281104d181460 /arch/x86/platform
parent079544ec60fcba3f32e4b513442cc131211c8e22 (diff)
downloadlinux-2cf615a4519b29a3ad283883d7638279ec1e6b44.tar.xz
x86/platform/intel-mid: Switch to new Intel CPU model defines
New CPU #defines encode vendor and family as well as model. N.B. Drop Haswell. CPU model 0x3C was included by mistake in upstream code. Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Acked-by: Andy Shevchenko <andy@kernel.org> Link: https://lore.kernel.org/all/20240521161002.12866-1-tony.luck%40intel.com
Diffstat (limited to 'arch/x86/platform')
-rw-r--r--arch/x86/platform/intel-mid/intel-mid.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/x86/platform/intel-mid/intel-mid.c b/arch/x86/platform/intel-mid/intel-mid.c
index 7be71c2cdc83..f83bbe0acd4a 100644
--- a/arch/x86/platform/intel-mid/intel-mid.c
+++ b/arch/x86/platform/intel-mid/intel-mid.c
@@ -22,6 +22,7 @@
#include <asm/mpspec_def.h>
#include <asm/hw_irq.h>
#include <asm/apic.h>
+#include <asm/cpu_device_id.h>
#include <asm/io_apic.h>
#include <asm/intel-mid.h>
#include <asm/io.h>
@@ -55,9 +56,8 @@ static void __init intel_mid_time_init(void)
static void intel_mid_arch_setup(void)
{
- switch (boot_cpu_data.x86_model) {
- case 0x3C:
- case 0x4A:
+ switch (boot_cpu_data.x86_vfm) {
+ case INTEL_ATOM_SILVERMONT_MID:
x86_platform.legacy.rtc = 1;
break;
default: