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authorIngo Molnar <mingo@elte.hu>2009-03-13 03:33:21 +0300
committerIngo Molnar <mingo@elte.hu>2009-03-13 03:33:21 +0300
commit480c93df5b99699390f93a7024c9f60d09da0e96 (patch)
treeb93b6c8c71c5f2e716dd05b126e01ef4e20ff0af /arch/x86/mm
parentaecfcde920da8d32949f6cbbc1fc051b4ef9e7be (diff)
parentd820ac4c2fa881079e6b689d2098adce337558ae (diff)
downloadlinux-480c93df5b99699390f93a7024c9f60d09da0e96.tar.xz
Merge branch 'core/locking' into tracing/ftrace
Diffstat (limited to 'arch/x86/mm')
-rw-r--r--arch/x86/mm/pageattr.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c
index 8253bc97587e..9c4294986af7 100644
--- a/arch/x86/mm/pageattr.c
+++ b/arch/x86/mm/pageattr.c
@@ -522,6 +522,17 @@ static int split_large_page(pte_t *kpte, unsigned long address)
* primary protection behavior:
*/
__set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE)));
+
+ /*
+ * Intel Atom errata AAH41 workaround.
+ *
+ * The real fix should be in hw or in a microcode update, but
+ * we also probabilistically try to reduce the window of having
+ * a large TLB mixed with 4K TLBs while instruction fetches are
+ * going on.
+ */
+ __flush_tlb_all();
+
base = NULL;
out_unlock: