diff options
| author | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2018-06-29 22:31:12 +0300 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2018-07-03 14:08:21 +0300 |
| commit | d99e5da91b36db5c35ddaf3653b280ee060971da (patch) | |
| tree | ef363bb4b801c96e006f75f3cbae52d8cb7e8d5c /arch/x86/kernel/tsc_msr.c | |
| parent | 5067b087cf5b2fa4de00443cdc6a66acb28a4953 (diff) | |
| download | linux-d99e5da91b36db5c35ddaf3653b280ee060971da.tar.xz | |
x86/platform/intel-mid: Remove custom TSC calibration
Since the commit
7da7c1561366 ("x86, tsc: Add static (MSR) TSC calibration on Intel Atom SoCs")
introduced a common way for all Intel MID chips to get their TSC frequency
via MSRs, there is no need to keep a duplication in each of Intel MID
platform code.
Thus, remove the custom calibration code for good.
Note, there is slight difference in how to get frequency for (reserved?)
values in MSRs, i.e. legacy code enforces some defaults while new code just
uses 0 in that cases.
Suggested-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Pavel Tatashin <pasha.tatashin@oracle.com>
Cc: Bin Gao <bin.gao@intel.com>
Link: https://lkml.kernel.org/r/20180629193113.84425-6-andriy.shevchenko@linux.intel.com
Diffstat (limited to 'arch/x86/kernel/tsc_msr.c')
| -rw-r--r-- | arch/x86/kernel/tsc_msr.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c index f0951c2e9f28..27ef714d886c 100644 --- a/arch/x86/kernel/tsc_msr.c +++ b/arch/x86/kernel/tsc_msr.c @@ -29,6 +29,11 @@ struct freq_desc { u32 freqs[MAX_NUM_FREQS]; }; +/* + * Penwell and Clovertrail use spread spectrum clock, + * so the freq number is not exactly the same as reported + * by MSR based on SDM. + */ static const struct freq_desc freq_desc_pnw = { 0, { 0, 0, 0, 0, 0, 99840, 0, 83200 } }; |