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| author | Ingo Molnar <mingo@elte.hu> | 2008-08-21 15:28:24 +0400 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-08-21 15:28:24 +0400 |
| commit | 470fba7ebe60ad9185056b080b331abad24b4df9 (patch) | |
| tree | f83bc13d97adaf5dd0e0f1d6a157b890f868577f /arch/sparc/include/asm/tsunami.h | |
| parent | 7225e75144b9718cbbe1820d9c011c809d5773fd (diff) | |
| parent | 6a55617ed5d1aa62b850de2cf66f5ede2eef4825 (diff) | |
| download | linux-470fba7ebe60ad9185056b080b331abad24b4df9.tar.xz | |
Merge branch 'linus' into x86/doc
Diffstat (limited to 'arch/sparc/include/asm/tsunami.h')
| -rw-r--r-- | arch/sparc/include/asm/tsunami.h | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/arch/sparc/include/asm/tsunami.h b/arch/sparc/include/asm/tsunami.h new file mode 100644 index 000000000000..5bbd1d523baa --- /dev/null +++ b/arch/sparc/include/asm/tsunami.h @@ -0,0 +1,64 @@ +/* + * tsunami.h: Module specific definitions for Tsunami V8 Sparcs + * + * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) + */ + +#ifndef _SPARC_TSUNAMI_H +#define _SPARC_TSUNAMI_H + +#include <asm/asi.h> + +/* The MMU control register on the Tsunami: + * + * ----------------------------------------------------------------------- + * | implvers |SW|AV|DV|MV| RSV |PC|ITD|ALC| RSV |PE| RC |IE|DE|RSV|NF|ME| + * ----------------------------------------------------------------------- + * 31 24 23 22 21 20 19-18 17 16 14 13-12 11 10-9 8 7 6-2 1 0 + * + * SW: Enable Software Table Walks 0=off 1=on + * AV: Address View bit + * DV: Data View bit + * MV: Memory View bit + * PC: Parity Control + * ITD: ITBR disable + * ALC: Alternate Cacheable + * PE: Parity Enable 0=off 1=on + * RC: Refresh Control + * IE: Instruction cache Enable 0=off 1=on + * DE: Data cache Enable 0=off 1=on + * NF: No Fault, same as all other SRMMUs + * ME: MMU Enable, same as all other SRMMUs + */ + +#define TSUNAMI_SW 0x00800000 +#define TSUNAMI_AV 0x00400000 +#define TSUNAMI_DV 0x00200000 +#define TSUNAMI_MV 0x00100000 +#define TSUNAMI_PC 0x00020000 +#define TSUNAMI_ITD 0x00010000 +#define TSUNAMI_ALC 0x00008000 +#define TSUNAMI_PE 0x00001000 +#define TSUNAMI_RCMASK 0x00000C00 +#define TSUNAMI_IENAB 0x00000200 +#define TSUNAMI_DENAB 0x00000100 +#define TSUNAMI_NF 0x00000002 +#define TSUNAMI_ME 0x00000001 + +static inline void tsunami_flush_icache(void) +{ + __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" + : /* no outputs */ + : "i" (ASI_M_IC_FLCLEAR) + : "memory"); +} + +static inline void tsunami_flush_dcache(void) +{ + __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" + : /* no outputs */ + : "i" (ASI_M_DC_FLCLEAR) + : "memory"); +} + +#endif /* !(_SPARC_TSUNAMI_H) */ |