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| author | Vincent Chen <vincent.chen@sifive.com> | 2021-04-29 10:58:36 +0300 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2021-05-06 19:40:13 +0300 |
| commit | 0e0d4992517fba81ecbceb5b71d2851f1208a02b (patch) | |
| tree | 8cec67f63e9caf3ce40fbaef266476eefb22c3aa /arch/riscv/mm/cacheflush.c | |
| parent | 8db6f937f4e76d9dd23795311fc14f0a5c0ac119 (diff) | |
| download | linux-0e0d4992517fba81ecbceb5b71d2851f1208a02b.tar.xz | |
riscv: enable SiFive errata CIP-453 and CIP-1200 Kconfig only if CONFIG_64BIT=y
The corresponding hardware issues of CONFIG_ERRATA_SIFIVE_CIP_453 and
CONFIG_ERRATA_SIFIVE_CIP_1200 only exist in the SiFive 64bit CPU cores.
Therefore, these two errata are required only if CONFIG_64BIT=y
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Fixes: bff3ff525460 ("riscv: sifive: Apply errata "cip-1200" patch")
Fixes: 800149a77c2c ("riscv: sifive: Apply errata "cip-453" patch")
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'arch/riscv/mm/cacheflush.c')
0 files changed, 0 insertions, 0 deletions