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| author | Anup Patel <apatel@ventanamicro.com> | 2023-03-28 06:52:17 +0300 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2023-04-08 13:26:23 +0300 |
| commit | 3ee92565b83ecc08e5b0c878dd87a2973eaca2ea (patch) | |
| tree | e1ed67069e6835bec9825cc9e5d9425770e71f07 /arch/riscv/kernel/sbi.c | |
| parent | 197b6b60ae7bc51dd0814953c562833143b292aa (diff) | |
| download | linux-3ee92565b83ecc08e5b0c878dd87a2973eaca2ea.tar.xz | |
RISC-V: Clear SIP bit only when using SBI IPI operations
The software interrupt pending (i.e. [M|S]SIP) bit is writeable for
S-mode but read-only for M-mode so we clear this bit only when using
SBI IPI operations.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20230328035223.1480939-2-apatel@ventanamicro.com
Diffstat (limited to 'arch/riscv/kernel/sbi.c')
| -rw-r--r-- | arch/riscv/kernel/sbi.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index 5c87db8fdff2..ac99a70ead6a 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -646,8 +646,14 @@ static void sbi_send_cpumask_ipi(const struct cpumask *target) sbi_send_ipi(target); } +static void sbi_ipi_clear(void) +{ + csr_clear(CSR_IP, IE_SIE); +} + static const struct riscv_ipi_ops sbi_ipi_ops = { - .ipi_inject = sbi_send_cpumask_ipi + .ipi_inject = sbi_send_cpumask_ipi, + .ipi_clear = sbi_ipi_clear }; void __init sbi_init(void) |