diff options
| author | Christoph Hellwig <hch@lst.de> | 2019-10-28 15:10:36 +0300 |
|---|---|---|
| committer | Paul Walmsley <paul.walmsley@sifive.com> | 2019-11-14 00:24:21 +0300 |
| commit | 8bf90f320d9ab4d642cdc0c1c5f05e8aa0a68db6 (patch) | |
| tree | 77164acfa1d0b97b5cfe175623210ee838279136 /arch/riscv/include/asm/sbi.h | |
| parent | 3320648ecc38190caad298fbbce949f591a10253 (diff) | |
| download | linux-8bf90f320d9ab4d642cdc0c1c5f05e8aa0a68db6.tar.xz | |
riscv: implement remote sfence.i using IPIs
The RISC-V ISA only supports flushing the instruction cache for the
local CPU core. Currently we always offload the remote TLB flushing to
the SBI, which then issues an IPI under the hoods. But with M-mode
we do not have an SBI so we have to do it ourselves. IPI to the
other nodes using the existing kernel helpers instead if we have
native clint support and thus can IPI directly from the kernel.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
[paul.walmsley@sifive.com: cleaned up code comment]
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Diffstat (limited to 'arch/riscv/include/asm/sbi.h')
| -rw-r--r-- | arch/riscv/include/asm/sbi.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index b167af3e7470..204af718df61 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -94,5 +94,8 @@ static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask, { SBI_CALL_4(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask, start, size, asid); } +#else /* CONFIG_RISCV_SBI */ +/* stub for code that is only reachable under IS_ENABLED(CONFIG_RISCV_SBI): */ +void sbi_remote_fence_i(const unsigned long *hart_mask); #endif /* CONFIG_RISCV_SBI */ #endif /* _ASM_RISCV_SBI_H */ |