diff options
| author | Paul Mackerras <paulus@samba.org> | 2008-06-09 08:01:46 +0400 |
|---|---|---|
| committer | Paul Mackerras <paulus@samba.org> | 2008-06-10 15:40:22 +0400 |
| commit | 917f0af9e5a9ceecf9e72537fabb501254ba321d (patch) | |
| tree | 1ef207755c6d83ce4af93ef2b5e4645eebd65886 /arch/ppc/boot/simple/rw4 | |
| parent | 0f3d6bcd391b058c619fc30e8022e8a29fbf4bef (diff) | |
| download | linux-917f0af9e5a9ceecf9e72537fabb501254ba321d.tar.xz | |
powerpc: Remove arch/ppc and include/asm-ppc
All the maintained platforms are now in arch/powerpc, so the old
arch/ppc stuff can now go away.
Acked-by: Adrian Bunk <bunk@kernel.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Becky Bruce <becky.bruce@freescale.com>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Acked-by: Jochen Friedrich <jochen@scram.de>
Acked-by: John Linn <john.linn@xilinx.com>
Acked-by: Jon Loeliger <jdl@freescale.com>
Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Olof Johansson <olof@lixom.net>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
Acked-by: Scott Wood <scottwood@freescale.com>
Acked-by: Sean MacLennan <smaclennan@pikatech.com>
Acked-by: Segher Boessenkool <segher@kernel.crashing.org>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com>
Acked-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/ppc/boot/simple/rw4')
| -rw-r--r-- | arch/ppc/boot/simple/rw4/ppc_40x.h | 664 | ||||
| -rw-r--r-- | arch/ppc/boot/simple/rw4/rw4_init.S | 78 | ||||
| -rw-r--r-- | arch/ppc/boot/simple/rw4/rw4_init_brd.S | 1125 | ||||
| -rw-r--r-- | arch/ppc/boot/simple/rw4/stb.h | 239 |
4 files changed, 0 insertions, 2106 deletions
diff --git a/arch/ppc/boot/simple/rw4/ppc_40x.h b/arch/ppc/boot/simple/rw4/ppc_40x.h deleted file mode 100644 index 561fb26f5a93..000000000000 --- a/arch/ppc/boot/simple/rw4/ppc_40x.h +++ /dev/null @@ -1,664 +0,0 @@ -/*----------------------------------------------------------------------------+ -| This source code has been made available to you by IBM on an AS-IS -| basis. Anyone receiving this source is licensed under IBM -| copyrights to use it in any way he or she deems fit, including -| copying it, modifying it, compiling it, and redistributing it either -| with or without modifications. No license under IBM patents or -| patent applications is to be implied by the copyright license. -| -| Any user of this software should understand that IBM cannot provide -| technical support for this software and will not be responsible for -| any consequences resulting from the use of this software. -| -| Any person who transfers this source code or any derivative work -| must include the IBM copyright notice, this paragraph, and the -| preceding two paragraphs in the transferred software. -| -| COPYRIGHT I B M CORPORATION 1997 -| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M -+----------------------------------------------------------------------------*/ -/*----------------------------------------------------------------------------+ -| Author: Tony J. Cerreto -| Component: Assembler include file. -| File: ppc_40x.h -| Purpose: Include file containing PPC DCR defines. -| -| Changes: -| Date Author Comment -| --------- ------ -------------------------------------------------------- -| 01-Mar-00 tjc Created -+----------------------------------------------------------------------------*/ -/* added by linguohui*/ -#define MW -/*----------------------------------------------------------------------------+ -| PPC Special purpose registers Numbers -+----------------------------------------------------------------------------*/ -#define ccr0 0x3b3 /* core configuration reg */ -#define ctr 0x009 /* count register */ -#define ctrreg 0x009 /* count register */ -#define dbcr0 0x3f2 /* debug control register 0 */ -#define dbcr1 0x3bd /* debug control register 1 */ -#define dbsr 0x3f0 /* debug status register */ -#define dccr 0x3fa /* data cache control reg. */ -#define dcwr 0x3ba /* data cache write-thru reg */ -#define dear 0x3d5 /* data exception address reg */ -#define esr 0x3d4 /* exception syndrome register */ -#define evpr 0x3d6 /* exception vector prefix reg */ -#define iccr 0x3fb /* instruction cache cntrl re */ -#define icdbdr 0x3d3 /* instr cache dbug data reg */ -#define lrreg 0x008 /* link register */ -#define pid 0x3b1 /* process id reg */ -#define pit 0x3db /* programmable interval time */ -#define pvr 0x11f /* processor version register */ -#define sgr 0x3b9 /* storage guarded reg */ -#define sler 0x3bb /* storage little endian reg */ -#define sprg0 0x110 /* special general purpose 0 */ -#define sprg1 0x111 /* special general purpose 1 */ -#define sprg2 0x112 /* special general purpose 2 */ -#define sprg3 0x113 /* special general purpose 3 */ -#define sprg4 0x114 /* special general purpose 4 */ -#define sprg5 0x115 /* special general purpose 5 */ -#define sprg6 0x116 /* special general purpose 6 */ -#define sprg7 0x117 /* special general purpose 7 */ -#define srr0 0x01a /* save/restore register 0 */ -#define srr1 0x01b /* save/restore register 1 */ -#define srr2 0x3de /* save/restore register 2 */ -#define srr3 0x3df /* save/restore register 3 */ -#define tbhi 0x11D -#define tblo 0x11C -#define tcr 0x3da /* timer control register */ -#define tsr 0x3d8 /* timer status register */ -#define xerreg 0x001 /* fixed point exception */ -#define xer 0x001 /* fixed point exception */ -#define zpr 0x3b0 /* zone protection reg */ - -/*----------------------------------------------------------------------------+ -| Decompression Controller -+----------------------------------------------------------------------------*/ -#define kiar 0x014 /* Decompression cntl addr reg */ -#define kidr 0x015 /* Decompression cntl data reg */ -#define kitor0 0x00 /* index table origin Reg 0 */ -#define kitor1 0x01 /* index table origin Reg 1 */ -#define kitor2 0x02 /* index table origin Reg 2 */ -#define kitor3 0x03 /* index table origin Reg 3 */ -#define kaddr0 0x04 /* addr decode Definition Reg 0 */ -#define kaddr1 0x05 /* addr decode Definition Reg 1 */ -#define kconf 0x40 /* Decompression cntl config reg */ -#define kid 0x41 /* Decompression cntl id reg */ -#define kver 0x42 /* Decompression cntl ver number */ -#define kpear 0x50 /* bus error addr reg (PLB) */ -#define kbear 0x51 /* bus error addr reg (DCP-EBC) */ -#define kesr0 0x52 /* bus error status reg 0 */ - -/*----------------------------------------------------------------------------+ -| Romeo Specific Device Control Register Numbers. -+----------------------------------------------------------------------------*/ -#ifndef VESTA -#define cdbcr 0x3d7 /* cache debug cntrl reg */ - -#define a_latcnt 0x1a9 /* PLB Latency count */ -#define a_tgval 0x1ac /* tone generation value */ -#define a_plb_pr 0x1bf /* PLB priority */ - -#define cic_sel1 0x031 /* select register 1 */ -#define cic_sel2 0x032 /* select register 2 */ - -#define clkgcrst 0x122 /* chip reset register */ - -#define cp_cpmsr 0x100 /*rstatus register */ -#define cp_cpmer 0x101 /* enable register */ - -#define dcp_kiar 0x190 /* indirect address register */ -#define dcp_kidr 0x191 /* indirect data register */ - -#define hsmc_mcgr 0x1c0 /* HSMC global register */ -#define hsmc_mcbesr 0x1c1 /* bus error status register */ -#define hsmc_mcbear 0x1c2 /* bus error address register*/ -#define hsmc_mcbr0 0x1c4 /* SDRAM sub-ctrl bank reg 0 */ -#define hsmc_mccr0 0x1c5 /* SDRAM sub-ctrl ctrl reg 0 */ -#define hsmc_mcbr1 0x1c7 /* SDRAM sub-ctrl bank reg 1 */ -#define hsmc_mccr1 0x1c8 /* SDRAM sub-ctrl ctrl reg 1 */ -#define hsmc_sysr 0x1d1 /* system register */ -#define hsmc_data 0x1d2 /* data register */ -#define hsmc_mccrr 0x1d3 /* refresh register */ - -#define ocm_pbar 0x1E0 /* base address register */ - -#define plb0_pacr0 0x057 /* PLB arbiter control reg */ -#define plb1_pacr1 0x067 /* PLB arbiter control reg */ - -#define v_displb 0x157 /* set left border of display*/ -#define v_disptb 0x158 /* top border of display */ -#define v_osd_la 0x159 /* first link address for OSD*/ -#define v_ptsdlta 0x15E /* PTS delta register */ -#define v_v0base 0x16C /* base mem add for VBI-0 */ -#define v_v1base 0x16D /* base mem add for VBI-1 */ -#define v_osbase 0x16E /* base mem add for OSD data */ -#endif - -/*----------------------------------------------------------------------------+ -| Vesta Device Control Register Numbers. -+----------------------------------------------------------------------------*/ -/*----------------------------------------------------------------------------+ -| Cross bar switch. -+----------------------------------------------------------------------------*/ -#define cbs0_cr 0x010 /* CBS configuration register */ - -/*----------------------------------------------------------------------------+ -| DCR external master (DCRX). -+----------------------------------------------------------------------------*/ -#define dcrx0_icr 0x020 /* internal control register */ -#define dcrx0_isr 0x021 /* internal status register */ -#define dcrx0_ecr 0x022 /* external control register */ -#define dcrx0_esr 0x023 /* external status register */ -#define dcrx0_tar 0x024 /* target address register */ -#define dcrx0_tdr 0x025 /* target data register */ -#define dcrx0_igr 0x026 /* interrupt generation register */ -#define dcrx0_bcr 0x027 /* buffer control register */ - -/*----------------------------------------------------------------------------+ -| Chip interconnect configuration. -+----------------------------------------------------------------------------*/ -#define cic0_cr 0x030 /* CIC control register */ -#define cic0_vcr 0x033 /* video macro control reg */ -#define cic0_sel3 0x035 /* select register 3 */ - -/*----------------------------------------------------------------------------+ -| Chip interconnect configuration. -+----------------------------------------------------------------------------*/ -#define sgpo0_sgpO 0x036 /* simplified GPIO output */ -#define sgpo0_gpod 0x037 /* simplified GPIO open drain */ -#define sgpo0_gptc 0x038 /* simplified GPIO tristate cntl */ -#define sgpo0_gpi 0x039 /* simplified GPIO input */ - -/*----------------------------------------------------------------------------+ -| Universal interrupt controller. -+----------------------------------------------------------------------------*/ -#define uic0_sr 0x040 /* status register */ -#define uic0_srs 0x041 /* status register set */ -#define uic0_er 0x042 /* enable register */ -#define uic0_cr 0x043 /* critical register */ -#define uic0_pr 0x044 /* parity register */ -#define uic0_tr 0x045 /* triggering register */ -#define uic0_msr 0x046 /* masked status register */ -#define uic0_vr 0x047 /* vector register */ -#define uic0_vcr 0x048 /* enable config register */ - -/*----------------------------------------------------------------------------+ -| PLB 0 and 1. -+----------------------------------------------------------------------------*/ -#define pb0_pesr 0x054 /* PLB error status reg 0 */ -#define pb0_pesrs 0x055 /* PLB error status reg 0 set */ -#define pb0_pear 0x056 /* PLB error address reg */ - -#define pb1_pesr 0x064 /* PLB error status reg 1 */ -#define pb1_pesrs 0x065 /* PLB error status reg 1 set */ -#define pb1_pear 0x066 /* PLB error address reg */ - -/*----------------------------------------------------------------------------+ -| EBIU DCR registers. -+----------------------------------------------------------------------------*/ -#define ebiu0_brcrh0 0x070 /* bus region register 0 high */ -#define ebiu0_brcrh1 0x071 /* bus region register 1 high */ -#define ebiu0_brcrh2 0x072 /* bus region register 2 high */ -#define ebiu0_brcrh3 0x073 /* bus region register 3 high */ -#define ebiu0_brcrh4 0x074 /* bus region register 4 high */ -#define ebiu0_brcrh5 0x075 /* bus region register 5 high */ -#define ebiu0_brcrh6 0x076 /* bus region register 6 high */ -#define ebiu0_brcrh7 0x077 /* bus region register 7 high */ -#define ebiu0_brcr0 0x080 /* bus region register 0 */ -#define ebiu0_brcr1 0x081 /* bus region register 1 */ -#define ebiu0_brcr2 0x082 /* bus region register 2 */ -#define ebiu0_brcr3 0x083 /* bus region register 3 */ -#define ebiu0_brcr4 0x084 /* bus region register 4 */ -#define ebiu0_brcr5 0x085 /* bus region register 5 */ -#define ebiu0_brcr6 0x086 /* bus region register 6 */ -#define ebiu0_brcr7 0x087 /* bus region register 7 */ -#define ebiu0_bear 0x090 /* bus error address register */ -#define ebiu0_besr 0x091 /* bus error syndrome reg */ -#define ebiu0_besr0s 0x093 /* bus error syndrome reg */ -#define ebiu0_biucr 0x09a /* bus interface control reg */ - -/*----------------------------------------------------------------------------+ -| OPB bridge. -+----------------------------------------------------------------------------*/ -#define opbw0_gesr 0x0b0 /* error status reg */ -#define opbw0_gesrs 0x0b1 /* error status reg */ -#define opbw0_gear 0x0b2 /* error address reg */ - -/*----------------------------------------------------------------------------+ -| DMA. -+----------------------------------------------------------------------------*/ -#define dma0_cr0 0x0c0 /* DMA channel control reg 0 */ -#define dma0_ct0 0x0c1 /* DMA count register 0 */ -#define dma0_da0 0x0c2 /* DMA destination addr reg 0 */ -#define dma0_sa0 0x0c3 /* DMA source addr register 0 */ -#define dma0_cc0 0x0c4 /* DMA chained count 0 */ -#define dma0_cr1 0x0c8 /* DMA channel control reg 1 */ -#define dma0_ct1 0x0c9 /* DMA count register 1 */ -#define dma0_da1 0x0ca /* DMA destination addr reg 1 */ -#define dma0_sa1 0x0cb /* DMA source addr register 1 */ -#define dma0_cc1 0x0cc /* DMA chained count 1 */ -#define dma0_cr2 0x0d0 /* DMA channel control reg 2 */ -#define dma0_ct2 0x0d1 /* DMA count register 2 */ -#define dma0_da2 0x0d2 /* DMA destination addr reg 2 */ -#define dma0_sa2 0x0d3 /* DMA source addr register 2 */ -#define dma0_cc2 0x0d4 /* DMA chained count 2 */ -#define dma0_cr3 0x0d8 /* DMA channel control reg 3 */ -#define dma0_ct3 0x0d9 /* DMA count register 3 */ -#define dma0_da3 0x0da /* DMA destination addr reg 3 */ -#define dma0_sa3 0x0db /* DMA source addr register 3 */ -#define dma0_cc3 0x0dc /* DMA chained count 3 */ -#define dma0_sr 0x0e0 /* DMA status register */ -#define dma0_srs 0x0e1 /* DMA status register */ -#define dma0_s1 0x031 /* DMA select1 register */ -#define dma0_s2 0x032 /* DMA select2 register */ - -/*---------------------------------------------------------------------------+ -| Clock and power management. -+----------------------------------------------------------------------------*/ -#define cpm0_fr 0x102 /* force register */ - -/*----------------------------------------------------------------------------+ -| Serial Clock Control. -+----------------------------------------------------------------------------*/ -#define ser0_ccr 0x120 /* serial clock control register */ - -/*----------------------------------------------------------------------------+ -| Audio Clock Control. -+----------------------------------------------------------------------------*/ -#define aud0_apcr 0x121 /* audio clock ctrl register */ - -/*----------------------------------------------------------------------------+ -| DENC. -+----------------------------------------------------------------------------*/ -#define denc0_idr 0x130 /* DENC ID register */ -#define denc0_cr1 0x131 /* control register 1 */ -#define denc0_rr1 0x132 /* microvision 1 (reserved 1) */ -#define denc0_cr2 0x133 /* control register 2 */ -#define denc0_rr2 0x134 /* microvision 2 (reserved 2) */ -#define denc0_rr3 0x135 /* microvision 3 (reserved 3) */ -#define denc0_rr4 0x136 /* microvision 4 (reserved 4) */ -#define denc0_rr5 0x137 /* microvision 5 (reserved 5) */ -#define denc0_ccdr 0x138 /* closed caption data */ -#define denc0_cccr 0x139 /* closed caption control */ -#define denc0_trr 0x13A /* teletext request register */ -#define denc0_tosr 0x13B /* teletext odd field line se */ -#define denc0_tesr 0x13C /* teletext even field line s */ -#define denc0_rlsr 0x13D /* RGB rhift left register */ -#define denc0_vlsr 0x13E /* video level shift register */ -#define denc0_vsr 0x13F /* video scaling register */ - -/*----------------------------------------------------------------------------+ -| Video decoder. Suspect 0x179, 0x169, 0x16a, 0x152 (rc). -+----------------------------------------------------------------------------*/ -#define vid0_ccntl 0x140 /* control decoder operation */ -#define vid0_cmode 0x141 /* video operational mode */ -#define vid0_sstc0 0x142 /* STC high order bits 31:0 */ -#define vid0_sstc1 0x143 /* STC low order bit 32 */ -#define vid0_spts0 0x144 /* PTS high order bits 31:0 */ -#define vid0_spts1 0x145 /* PTS low order bit 32 */ -#define vid0_fifo 0x146 /* FIFO data port */ -#define vid0_fifos 0x147 /* FIFO status */ -#define vid0_cmd 0x148 /* send command to decoder */ -#define vid0_cmdd 0x149 /* port for command params */ -#define vid0_cmdst 0x14A /* command status */ -#define vid0_cmdad 0x14B /* command address */ -#define vid0_procia 0x14C /* instruction store */ -#define vid0_procid 0x14D /* data port for I_Store */ -#define vid0_osdm 0x151 /* OSD mode control */ -#define vid0_hosti 0x152 /* base interrupt register */ -#define vid0_mask 0x153 /* interrupt mask register */ -#define vid0_dispm 0x154 /* operational mode for Disp */ -#define vid0_dispd 0x155 /* setting for 'Sync' delay */ -#define vid0_vbctl 0x156 /* VBI */ -#define vid0_ttxctl 0x157 /* teletext control */ -#define vid0_disptb 0x158 /* display left/top border */ -#define vid0_osdgla 0x159 /* Graphics plane link addr */ -#define vid0_osdila 0x15A /* Image plane link addr */ -#define vid0_rbthr 0x15B /* rate buffer threshold */ -#define vid0_osdcla 0x15C /* Cursor link addr */ -#define vid0_stcca 0x15D /* STC common address */ -#define vid0_ptsctl 0x15F /* PTS Control */ -#define vid0_wprot 0x165 /* write protect for I_Store */ -#define vid0_vcqa 0x167 /* video clip queued block Ad */ -#define vid0_vcql 0x168 /* video clip queued block Le */ -#define vid0_blksz 0x169 /* block size bytes for copy op */ -#define vid0_srcad 0x16a /* copy source address bits 6-31 */ -#define vid0_udbas 0x16B /* base mem add for user data */ -#define vid0_vbibas 0x16C /* base mem add for VBI 0/1 */ -#define vid0_osdibas 0x16D /* Image plane base address */ -#define vid0_osdgbas 0x16E /* Graphic plane base address */ -#define vid0_rbbase 0x16F /* base mem add for video buf */ -#define vid0_dramad 0x170 /* DRAM address */ -#define vid0_dramdt 0x171 /* data port for DRAM access */ -#define vid0_dramcs 0x172 /* DRAM command and statusa */ -#define vid0_vcwa 0x173 /* v clip work address */ -#define vid0_vcwl 0x174 /* v clip work length */ -#define vid0_mseg0 0x175 /* segment address 0 */ -#define vid0_mseg1 0x176 /* segment address 1 */ -#define vid0_mseg2 0x177 /* segment address 2 */ -#define vid0_mseg3 0x178 /* segment address 3 */ -#define vid0_fbbase 0x179 /* frame buffer base memory */ -#define vid0_osdcbas 0x17A /* Cursor base addr */ -#define vid0_lboxtb 0x17B /* top left border */ -#define vid0_trdly 0x17C /* transparency gate delay */ -#define vid0_sbord 0x17D /* left/top small pict. bord. */ -#define vid0_zoffs 0x17E /* hor/ver zoom window */ -#define vid0_rbsz 0x17F /* rate buffer size read */ - -/*----------------------------------------------------------------------------+ -| Transport demultiplexer. -+----------------------------------------------------------------------------*/ -#define xpt0_lr 0x180 /* demux location register */ -#define xpt0_data 0x181 /* demux data register */ -#define xpt0_ir 0x182 /* demux interrupt register */ - -#define xpt0_config1 0x0000 /* configuration 1 */ -#define xpt0_control1 0x0001 /* control 1 */ -#define xpt0_festat 0x0002 /* Front-end status */ -#define xpt0_feimask 0x0003 /* Front_end interrupt Mask */ -#define xpt0_ocmcnfg 0x0004 /* OCM Address */ -#define xpt0_settapi 0x0005 /* Set TAP Interrupt */ - -#define xpt0_pcrhi 0x0010 /* PCR High */ -#define xpt0_pcrlow 0x0011 /* PCR Low */ -#define xpt0_lstchi 0x0012 /* Latched STC High */ -#define xpt0_lstclow 0x0013 /* Latched STC Low */ -#define xpt0_stchi 0x0014 /* STC High */ -#define xpt0_stclow 0x0015 /* STC Low */ -#define xpt0_pwm 0x0016 /* PWM */ -#define xpt0_pcrstct 0x0017 /* PCR-STC Threshold */ -#define xpt0_pcrstcd 0x0018 /* PCR-STC Delta */ -#define xpt0_stccomp 0x0019 /* STC Compare */ -#define xpt0_stccmpd 0x001a /* STC Compare Disarm */ - -#define xpt0_dsstat 0x0048 /* Descrambler Status */ -#define xpt0_dsimask 0x0049 /* Descrambler Interrupt Mask */ - -#define xpt0_vcchng 0x01f0 /* Video Channel Change */ -#define xpt0_acchng 0x01f1 /* Audio Channel Change */ -#define xpt0_axenable 0x01fe /* Aux PID Enables */ -#define xpt0_pcrpid 0x01ff /* PCR PID */ - -#define xpt0_config2 0x1000 /* Configuration 2 */ -#define xpt0_pbuflvl 0x1002 /* Packet Buffer Level */ -#define xpt0_intmask 0x1003 /* Interrupt Mask */ -#define xpt0_plbcnfg 0x1004 /* PLB Configuration */ - -#define xpt0_qint 0x1010 /* Queues Interrupts */ -#define xpt0_qintmsk 0x1011 /* Queues Interrupts Mask */ -#define xpt0_astatus 0x1012 /* Audio Status */ -#define xpt0_aintmask 0x1013 /* Audio Interrupt Mask */ -#define xpt0_vstatus 0x1014 /* Video Status */ -#define xpt0_vintmask 0x1015 /* Video Interrupt Mask */ - -#define xpt0_qbase 0x1020 /* Queue Base */ -#define xpt0_bucketq 0x1021 /* Bucket Queue */ -#define xpt0_qstops 0x1024 /* Queue Stops */ -#define xpt0_qresets 0x1025 /* Queue Resets */ -#define xpt0_sfchng 0x1026 /* Section Filter Change */ - -/*----------------------------------------------------------------------------+ -| Audio decoder. Suspect 0x1ad, 0x1b4, 0x1a3, 0x1a5 (read/write status) -+----------------------------------------------------------------------------*/ -#define aud0_ctrl0 0x1a0 /* control 0 */ -#define aud0_ctrl1 0x1a1 /* control 1 */ -#define aud0_ctrl2 0x1a2 /* control 2 */ -#define aud0_cmd 0x1a3 /* command register */ -#define aud0_isr 0x1a4 /* interrupt status register */ -#define aud0_imr 0x1a5 /* interrupt mask register */ -#define aud0_dsr 0x1a6 /* decoder status register */ -#define aud0_stc 0x1a7 /* system time clock */ -#define aud0_csr 0x1a8 /* channel status register */ -#define aud0_lcnt 0x1a9 /* queued address register 2 */ -#define aud0_pts 0x1aa /* presentation time stamp */ -#define aud0_tgctrl 0x1ab /* tone generation control */ -#define aud0_qlr2 0x1ac /* queued length register 2 */ -#define aud0_auxd 0x1ad /* aux data */ -#define aud0_strmid 0x1ae /* stream ID */ -#define aud0_qar 0x1af /* queued address register */ -#define aud0_dsps 0x1b0 /* DSP status */ -#define aud0_qlr 0x1b1 /* queued len address */ -#define aud0_dspc 0x1b2 /* DSP control */ -#define aud0_wlr2 0x1b3 /* working length register 2 */ -#define aud0_instd 0x1b4 /* instruction download */ -#define aud0_war 0x1b5 /* working address register */ -#define aud0_seg1 0x1b6 /* segment 1 base register */ -#define aud0_seg2 0x1b7 /* segment 2 base register */ -#define aud0_avf 0x1b9 /* audio att value front */ -#define aud0_avr 0x1ba /* audio att value rear */ -#define aud0_avc 0x1bb /* audio att value center */ -#define aud0_seg3 0x1bc /* segment 3 base register */ -#define aud0_offset 0x1bd /* offset address */ -#define aud0_wrl 0x1be /* working length register */ -#define aud0_war2 0x1bf /* working address register 2 */ - -/*----------------------------------------------------------------------------+ -| High speed memory controller 0 and 1. -+----------------------------------------------------------------------------*/ -#define hsmc0_gr 0x1e0 /* HSMC global register */ -#define hsmc0_besr 0x1e1 /* bus error status register */ -#define hsmc0_bear 0x1e2 /* bus error address register */ -#define hsmc0_br0 0x1e4 /* SDRAM sub-ctrl bank reg 0 */ -#define hsmc0_cr0 0x1e5 /* SDRAM sub-ctrl ctrl reg 0 */ -#define hsmc0_br1 0x1e7 /* SDRAM sub-ctrl bank reg 1 */ -#define hsmc0_cr1 0x1e8 /* SDRAM sub-ctrl ctrl reg 1 */ -#define hsmc0_sysr 0x1f1 /* system register */ -#define hsmc0_data 0x1f2 /* data register */ -#define hsmc0_crr 0x1f3 /* refresh register */ - -#define hsmc1_gr 0x1c0 /* HSMC global register */ -#define hsmc1_besr 0x1c1 /* bus error status register */ -#define hsmc1_bear 0x1c2 /* bus error address register */ -#define hsmc1_br0 0x1c4 /* SDRAM sub-ctrl bank reg 0 */ -#define hsmc1_cr0 0x1c5 /* SDRAM sub-ctrl ctrl reg 0 */ -#define hsmc1_br1 0x1c7 /* SDRAM sub-ctrl bank reg 1 */ -#define hsmc1_cr1 0x1c8 /* SDRAM sub-ctrl ctrl reg 1 */ -#define hsmc1_sysr 0x1d1 /* system register */ -#define hsmc1_data 0x1d2 /* data register */ -#define hsmc1_crr 0x1d3 /* refresh register */ - -/*----------------------------------------------------------------------------+ -| Machine State Register bit definitions. -+----------------------------------------------------------------------------*/ -#define msr_ape 0x00100000 -#define msr_apa 0x00080000 -#define msr_we 0x00040000 -#define msr_ce 0x00020000 -#define msr_ile 0x00010000 -#define msr_ee 0x00008000 -#define msr_pr 0x00004000 -#define msr_me 0x00001000 -#define msr_de 0x00000200 -#define msr_ir 0x00000020 -#define msr_dr 0x00000010 -#define msr_le 0x00000001 - -/*----------------------------------------------------------------------------+ -| Used during interrupt processing. -+----------------------------------------------------------------------------*/ -#define stack_reg_image_size 160 - -/*----------------------------------------------------------------------------+ -| Function prolog definition and other Metaware (EABI) defines. -+----------------------------------------------------------------------------*/ -#ifdef MW - -#define r0 0 -#define r1 1 -#define r2 2 -#define r3 3 -#define r4 4 -#define r5 5 -#define r6 6 -#define r7 7 -#define r8 8 -#define r9 9 -#define r10 10 -#define r11 11 -#define r12 12 -#define r13 13 -#define r14 14 -#define r15 15 -#define r16 16 -#define r17 17 -#define r18 18 -#define r19 19 -#define r20 20 -#define r21 21 -#define r22 22 -#define r23 23 -#define r24 24 -#define r25 25 -#define r26 26 -#define r27 27 -#define r28 28 -#define r29 29 -#define r30 30 -#define r31 31 - -#define cr0 0 -#define cr1 1 -#define cr2 2 -#define cr3 3 -#define cr4 4 -#define cr5 5 -#define cr6 6 -#define cr7 7 - -#define function_prolog(func_name) .text; \ - .align 2; \ - .globl func_name; \ - func_name: -#define function_epilog(func_name) .type func_name,@function; \ - .size func_name,.-func_name - -#define function_call(func_name) bl func_name - -#define stack_frame_min 8 -#define stack_frame_bc 0 -#define stack_frame_lr 4 -#define stack_neg_off 0 - -#endif - -/*----------------------------------------------------------------------------+ -| Function prolog definition and other DIAB (Elf) defines. -+----------------------------------------------------------------------------*/ -#ifdef ELF_DIAB - -fprolog: macro f_name - .text - .align 2 - .globl f_name -f_name: - endm - -fepilog: macro f_name - .type f_name,@function - .size f_name,.-f_name - endm - -#define function_prolog(func_name) fprolog func_name -#define function_epilog(func_name) fepilog func_name -#define function_call(func_name) bl func_name - -#define stack_frame_min 8 -#define stack_frame_bc 0 -#define stack_frame_lr 4 -#define stack_neg_off 0 - -#endif - -/*----------------------------------------------------------------------------+ -| Function prolog definition and other Xlc (XCOFF) defines. -+----------------------------------------------------------------------------*/ -#ifdef XCOFF - -.machine "403ga" - -#define r0 0 -#define r1 1 -#define r2 2 -#define r3 3 -#define r4 4 -#define r5 5 -#define r6 6 -#define r7 7 -#define r8 8 -#define r9 9 -#define r10 10 -#define r11 11 -#define r12 12 -#define r13 13 -#define r14 14 -#define r15 15 -#define r16 16 -#define r17 17 -#define r18 18 -#define r19 19 -#define r20 20 -#define r21 21 -#define r22 22 -#define r23 23 -#define r24 24 -#define r25 25 -#define r26 26 -#define r27 27 -#define r28 28 -#define r29 29 -#define r30 30 -#define r31 31 - -#define cr0 0 -#define cr1 1 -#define cr2 2 -#define cr3 3 -#define cr4 4 -#define cr5 5 -#define cr6 6 -#define cr7 7 - -#define function_prolog(func_name) .csect .func_name[PR]; \ - .globl .func_name[PR]; \ - func_name: - -#define function_epilog(func_name) .toc; \ - .csect func_name[DS]; \ - .globl func_name[DS]; \ - .long .func_name[PR]; \ - .long TOC[tc0] - -#define function_call(func_name) .extern .func_name[PR]; \ - stw r2,stack_frame_toc(r1); \ - mfspr r2,sprg0; \ - bl .func_name[PR]; \ - lwz r2,stack_frame_toc(r1) - -#define stack_frame_min 56 -#define stack_frame_bc 0 -#define stack_frame_lr 8 -#define stack_frame_toc 20 -#define stack_neg_off 276 - -#endif -#define function_prolog(func_name) .text; \ - .align 2; \ - .globl func_name; \ - func_name: -#define function_epilog(func_name) .type func_name,@function; \ - .size func_name,.-func_name - -#define function_call(func_name) bl func_name - -/*----------------------------------------------------------------------------+ -| Function prolog definition for GNU -+----------------------------------------------------------------------------*/ -#ifdef _GNU_TOOL - -#define function_prolog(func_name) .globl func_name; \ - func_name: -#define function_epilog(func_name) - -#endif diff --git a/arch/ppc/boot/simple/rw4/rw4_init.S b/arch/ppc/boot/simple/rw4/rw4_init.S deleted file mode 100644 index b1061962e46b..000000000000 --- a/arch/ppc/boot/simple/rw4/rw4_init.S +++ /dev/null @@ -1,78 +0,0 @@ -#define VESTA -#include "ppc_40x.h" -# - .align 2 - .text -# -# added by linguohui - .extern initb_ebiu0, initb_config, hdw_init_finish - .extern initb_hsmc0, initb_hsmc1, initb_cache -# end added - .globl HdwInit -# -HdwInit: -# -#-----------------------------------------------------------------------* -# If we are not executing from the FLASH get out * -#-----------------------------------------------------------------------* -# SAW keep this or comment out a la Hawthorne? -# r3 contains NIP when used with Linux -# rlwinm r28, r3, 8, 24, 31 # if MSB == 0xFF -> FLASH address -# cmpwi r28, 0xff -# bne locn01 -# -# -#------------------------------------------------------------------------ -# Init_cpu. Bank registers are setup for the IBM STB. -#------------------------------------------------------------------------ -# -# Setup processor core clock to be driven off chip. This is GPI4 bit -# twenty. Setup Open Drain, Output Select, Three-State Control, and -# Three-State Select registers. -# - - - pb0pesr = 0x054 - pb0pear = 0x056 - - mflr r30 - -#----------------------------------------------------------------------------- -# Vectors will be at 0x1F000000 -# Dummy Machine check handler just does RFI before true handler gets installed -#----------------------------------------------------------------------------- -#if 1 /* xuwentao added*/ -#ifdef SDRAM16MB - lis r10,0x0000 - addi r10,r10,0x0000 -#else - lis r10,0x1F00 - addi r10,r10,0x0000 -#endif - - mtspr evpr,r10 #EVPR: 0x0 or 0x1f000000 depending - isync # on SDRAM memory model used. - - lis r10,0xFFFF # clear PB0_PESR because some - ori r10,r10,0xFFFF # transitions from flash,changed by linguohui - mtdcr pb0pesr,r10 # to load RAM image via RiscWatch - lis r10,0x0000 # cause PB0_PESR machine checks - mtdcr pb0pear,r10 - addis r10,r10,0x0000 # clear the - mtxer r10 # XER just in case... -#endif /* xuwentao*/ - - bl initb_ebiu0 # init EBIU - - bl initb_config # config PPC and board - - - - -#------------------------------------------------------------------------ -# EVPR setup moved to top of this function. -#------------------------------------------------------------------------ -# - mtlr r30 - blr - .end diff --git a/arch/ppc/boot/simple/rw4/rw4_init_brd.S b/arch/ppc/boot/simple/rw4/rw4_init_brd.S deleted file mode 100644 index 386afdaad6c7..000000000000 --- a/arch/ppc/boot/simple/rw4/rw4_init_brd.S +++ /dev/null @@ -1,1125 +0,0 @@ -/*----------------------------------------------------------------------------+ -| This source code has been made available to you by IBM on an AS-IS -| basis. Anyone receiving this source is licensed under IBM -| copyrights to use it in any way he or she deems fit, including -| copying it, modifying it, compiling it, and redistributing it either -| with or without modifications. No license under IBM patents or -| patent applications is to be implied by the copyright license. -| -| Any user of this software should understand that IBM cannot provide -| technical support for this software and will not be responsible for -| any consequences resulting from the use of this software. -| -| Any person who transfers this source code or any derivative work -| must include the IBM copyright notice, this paragraph, and the -| preceding two paragraphs in the transferred software. -| -| COPYRIGHT I B M CORPORATION 1997 -| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M -+----------------------------------------------------------------------------*/ -/*----------------------------------------------------------------------------+ -| Author: Tony J. Cerreto -| Component: BSPS -| File: init_brd.s -| Purpose: Vesta Evaluation Board initialization subroutines. The following -| routines are available: -| 1. INITB_EBIU0: Initialize EBIU0. -| 2. INITB_CONFIG: Configure board. -| 3. INITB_HSMC0: Initialize HSMC0 (SDRAM). -| 4. INITB_HSMC1: Initialize HSMC1 (SDRAM). -| 5. INITB_CACHE: Initialize Data and Instruction Cache. -| 6. INITB_DCACHE: Initialize Data Cache. -| 7. INITB_ICACHE: Initialize Instruction Cache. -| 8. INITB_GET_CSPD: Get CPU Speed (Bus Speed and Processor Speed) -| -| Changes: -| Date: Author Comment: -| --------- ------ -------- -| 01-Mar-00 tjc Created -| 04-Mar-00 jfh Modified CIC_SEL3_VAL to support 1284 (Mux3 & GPIO 21-28) -| 04-Mar-00 jfh Modified XILINIX Reg 0 to support 1284 (Mux3 & GPIO 21-28) -| 04-Mar-00 jfh Modified XILINIX Reg 1 to support 1284 (Mux3 & GPIO 21-28) -| 04-Mar-00 jfh Modified XILINIX Reg 4 to support 1284 (Mux3 & GPIO 21-28) -| 19-May-00 rlb Relcoated HSMC0 to 0x1F000000 to support 32MB of contiguous -| SDRAM space. Changed cache ctl regs to reflect this. -| 22-May-00 tjc Changed initb_get_cspd interface and eliminated -| initb_get_bspd routines. -| 26-May-00 tjc Added two nop instructions after all mtxxx/mfxxx -| instructions due to PPC405 bug. -+----------------------------------------------------------------------------*/ -#define VESTA -#include "ppc_40x.h" -#include "stb.h" - -/*----------------------------------------------------------------------------+ -| BOARD CONFIGURATION DEFINES -+----------------------------------------------------------------------------*/ -#define CBS0_CR_VAL 0x00000002 /* CBS control reg value */ -#define CIC0_CR_VAL 0xD0800448 /* CIC control reg value */ -#define CIC0_SEL3_VAL 0x11500000 /* CIC select 3 reg value */ -#define CIC0_VCR_VAL 0x00631700 /* CIC video cntl reg value */ - -/*----------------------------------------------------------------------------+ -| EBIU0 BANK REGISTERS DEFINES -+----------------------------------------------------------------------------*/ -#define EBIU0_BRCRH0_VAL 0x00000000 /* BR High 0 (Extension Reg)*/ -#define EBIU0_BRCRH1_VAL 0x00000000 /* BR High 1 (Extension Reg)*/ -#define EBIU0_BRCRH2_VAL 0x40000000 /* BR High 2 (Extension Reg)*/ -#define EBIU0_BRCRH3_VAL 0x40000000 /* BR High 3 (Extension Reg)*/ -#define EBIU0_BRCRH4_VAL 0x00000000 /* BR High 4 (Extension Reg)*/ -#define EBIU0_BRCRH5_VAL 0x00000000 /* BR High 5 (Extension Reg)*/ -#define EBIU0_BRCRH6_VAL 0x00000000 /* BR High 6 (Extension Reg)*/ -#define EBIU0_BRCRH7_VAL 0x40000000 /* BR High 7 (Extension Reg)*/ - -#define EBIU0_BRCR0_VAL 0xFC58BFFE /* BR 0: 16 bit Flash 4 MB */ -#define EBIU0_BRCR1_VAL 0xFF00BFFE /* BR 1: Ext Connector 1 MB */ -#if 1 -#define EBIU0_BRCR2_VAL 0x207CFFBE /* BR 2: Xilinx 8 MB */ - /* twt == 0x3f */ -#else -#define EBIU0_BRCR2_VAL 0x207CCFBE /* BR 2: Xilinx 8 MB */ - /* twt == 0x0f */ -#endif -#define EBIU0_BRCR3_VAL 0x407CBFBE /* BR 3: IDE Drive 8 MB */ -#define EBIU0_BRCR4_VAL 0xFF00BFFF /* BR 4: Disabled. 0 MB */ -#define EBIU0_BRCR5_VAL 0xFF00BFFF /* BR 5: Disabled. 0 MB */ -#define EBIU0_BRCR6_VAL 0xFF00BFFF /* BR 6: Disabled. 0 MB */ -#define EBIU0_BRCR7_VAL 0xCE3F0003 /* BR 7: Line Mode DMA 2 MB */ - -/*----------------------------------------------------------------------------+ -| GPIO DEFINES -+----------------------------------------------------------------------------*/ -#define STB_GPIO0_OUTPUT (STB_GPIO0_BASE_ADDRESS+ 0x00) -#define STB_GPIO0_TC (STB_GPIO0_BASE_ADDRESS+ 0x04) -#define STB_GPIO0_OS_0_31 (STB_GPIO0_BASE_ADDRESS+ 0x08) -#define STB_GPIO0_OS_32_63 (STB_GPIO0_BASE_ADDRESS+ 0x0C) -#define STB_GPIO0_TS_0_31 (STB_GPIO0_BASE_ADDRESS+ 0x10) -#define STB_GPIO0_TS_32_63 (STB_GPIO0_BASE_ADDRESS+ 0x14) -#define STB_GPIO0_OD (STB_GPIO0_BASE_ADDRESS+ 0x18) -#define STB_GPIO0_INPUT (STB_GPIO0_BASE_ADDRESS+ 0x1C) -#define STB_GPIO0_R1 (STB_GPIO0_BASE_ADDRESS+ 0x20) -#define STB_GPIO0_R2 (STB_GPIO0_BASE_ADDRESS+ 0x24) -#define STB_GPIO0_R3 (STB_GPIO0_BASE_ADDRESS+ 0x28) -#define STB_GPIO0_IS_1_0_31 (STB_GPIO0_BASE_ADDRESS+ 0x30) -#define STB_GPIO0_IS_1_32_63 (STB_GPIO0_BASE_ADDRESS+ 0x34) -#define STB_GPIO0_IS_2_0_31 (STB_GPIO0_BASE_ADDRESS+ 0x38) -#define STB_GPIO0_IS_2_32_63 (STB_GPIO0_BASE_ADDRESS+ 0x3C) -#define STB_GPIO0_IS_3_0_31 (STB_GPIO0_BASE_ADDRESS+ 0x40) -#define STB_GPIO0_IS_3_32_63 (STB_GPIO0_BASE_ADDRESS+ 0x44) -#define STB_GPIO0_SS_1 (STB_GPIO0_BASE_ADDRESS+ 0x50) -#define STB_GPIO0_SS_2 (STB_GPIO0_BASE_ADDRESS+ 0x54) -#define STB_GPIO0_SS_3 (STB_GPIO0_BASE_ADDRESS+ 0x58) - -#define GPIO0_TC_VAL 0x0C020004 /* three-state control val */ -#define GPIO0_OS_0_31_VAL 0x51A00004 /* output select 0-31 val */ -#define GPIO0_OS_32_63_VAL 0x0000002F /* output select 32-63 val */ -#define GPIO0_TS_0_31_VAL 0x51A00000 /* three-state sel 0-31 val*/ -#define GPIO0_TS_32_63_VAL 0x0000000F /* three-state sel 32-63 val*/ -#define GPIO0_OD_VAL 0xC0000004 /* open drain val */ -#define GPIO0_IS_1_0_31_VAL 0x50000151 /* input select 1 0-31 val */ -#define GPIO0_IS_1_32_63_VAL 0x00000000 /* input select 1 32-63 val */ -#define GPIO0_IS_2_0_31_VAL 0x00000000 /* input select 2 0-31 val */ -#define GPIO0_IS_2_32_63_VAL 0x00000000 /* input select 2 32-63 val */ -#define GPIO0_IS_3_0_31_VAL 0x00000440 /* input select 3 0-31 val */ -#define GPIO0_IS_3_32_63_VAL 0x00000000 /* input select 3 32-63 val */ -#define GPIO0_SS_1_VAL 0x00000000 /* sync select 1 val */ -#define GPIO0_SS_2_VAL 0x00000000 /* sync select 2 val */ -#define GPIO0_SS_3_VAL 0x00000000 /* sync select 3 val */ - -/*----------------------------------------------------------------------------+ -| XILINX DEFINES -+----------------------------------------------------------------------------*/ -#define STB_XILINX_LED (STB_FPGA_BASE_ADDRESS+ 0x0100) -#define STB_XILINX1_REG0 (STB_FPGA_BASE_ADDRESS+ 0x40000) -#define STB_XILINX1_REG1 (STB_FPGA_BASE_ADDRESS+ 0x40002) -#define STB_XILINX1_REG2 (STB_FPGA_BASE_ADDRESS+ 0x40004) -#define STB_XILINX1_REG3 (STB_FPGA_BASE_ADDRESS+ 0x40006) -#define STB_XILINX1_REG4 (STB_FPGA_BASE_ADDRESS+ 0x40008) -#define STB_XILINX1_REG5 (STB_FPGA_BASE_ADDRESS+ 0x4000A) -#define STB_XILINX1_REG6 (STB_FPGA_BASE_ADDRESS+ 0x4000C) -#define STB_XILINX1_ID (STB_FPGA_BASE_ADDRESS+ 0x4000E) -#define STB_XILINX1_FLUSH (STB_FPGA_BASE_ADDRESS+ 0x4000E) -#define STB_XILINX2_REG0 (STB_FPGA_BASE_ADDRESS+ 0x80000) -#define STB_XILINX2_REG1 (STB_FPGA_BASE_ADDRESS+ 0x80002) -#define STB_XILINX2_REG2 (STB_FPGA_BASE_ADDRESS+ 0x80004) - -#define XILINX1_R0_VAL 0x2440 /* Xilinx 1 Register 0 Val */ -#define XILINX1_R1_VAL 0x0025 /* Xilinx 1 Register 1 Val */ -#define XILINX1_R2_VAL 0x0441 /* Xilinx 1 Register 2 Val */ -#define XILINX1_R3_VAL 0x0008 /* Xilinx 1 Register 3 Val */ -#define XILINX1_R4_VAL 0x0100 /* Xilinx 1 Register 4 Val */ -#define XILINX1_R5_VAL 0x6810 /* Xilinx 1 Register 5 Val */ -#define XILINX1_R6_VAL 0x0000 /* Xilinx 1 Register 6 Val */ -#if 0 -#define XILINX2_R0_VAL 0x0008 /* Xilinx 2 Register 0 Val */ -#define XILINX2_R1_VAL 0x0000 /* Xilinx 2 Register 1 Val */ -#else -#define XILINX2_R0_VAL 0x0018 /* disable IBM IrDA RxD */ -#define XILINX2_R1_VAL 0x0008 /* enable SICC MAX chip */ -#endif -#define XILINX2_R2_VAL 0x0000 /* Xilinx 2 Register 2 Val */ - -/*----------------------------------------------------------------------------+ -| HSMC BANK REGISTERS DEFINES -+----------------------------------------------------------------------------*/ -#ifdef SDRAM16MB -#define HSMC0_BR0_VAL 0x000D2D55 /* 0x1F000000-007FFFFF R/W */ -#define HSMC0_BR1_VAL 0x008D2D55 /* 0x1F800000-1FFFFFFF R/W */ -#else -#define HSMC0_BR0_VAL 0x1F0D2D55 /* 0x1F000000-007FFFFF R/W */ -#define HSMC0_BR1_VAL 0x1F8D2D55 /* 0x1F800000-1FFFFFFF R/W */ -#endif -#define HSMC1_BR0_VAL 0xA00D2D55 /* 0xA0000000-A07FFFFF R/W */ -#define HSMC1_BR1_VAL 0xA08D2D55 /* 0xA0800000-A0FFFFFF R/W */ - -/*----------------------------------------------------------------------------+ -| CACHE DEFINES -+----------------------------------------------------------------------------*/ -#define DCACHE_NLINES 128 /* no. D-cache lines */ -#define DCACHE_NBYTES 32 /* no. bytes/ D-cache line */ -#define ICACHE_NLINES 256 /* no. I-cache lines */ -#define ICACHE_NBYTES 32 /* no. bytes/ I-cache line */ -#ifdef SDRAM16MB -#define DCACHE_ENABLE 0x80000000 /* D-cache regions to enable*/ -#define ICACHE_ENABLE 0x80000001 /* I-cache regions to enable*/ -#else -#define DCACHE_ENABLE 0x18000000 /* D-cache regions to enable*/ -#define ICACHE_ENABLE 0x18000001 /* I-cache regions to enable*/ -#endif - -/*----------------------------------------------------------------------------+ -| CPU CORE SPEED CALCULATION DEFINES -+----------------------------------------------------------------------------*/ -#define GCS_LCNT 500000 /* CPU speed loop count */ -#define GCS_TROW_BYTES 8 /* no. bytes in table row */ -#define GCS_CTICK_TOL 100 /* allowable clock tick tol */ -#define GCS_NMULT 4 /* no. of core speed mults */ - - /*--------------------------------------------------------------------+ - | No. 13.5Mhz - | Clock Ticks - | based on a - | loop count Bus - | of 100,000 Speed - +--------------------------------------------------------------------*/ -gcs_lookup_table: - .int 50000, 54000000 /* 54.0 Mhz */ - .int 66667, 40500000 /* 40.5 Mhz */ - .int 54545, 49500000 /* 49.5 Mhz */ - .int 46154, 58500000 /* 58.5 Mhz */ - .int 0, 0 /* end of table flag */ - - -/*****************************************************************************+ -| XXXXXXX XXX XXX XXXXXX XXXXXXX XXXXXX XX XX XX XXXX -| XX X XX XX X XX X XX X XX XX XXX XX XXXX XX -| XX X XXX XX XX X XX XX XXXX XX XX XX XX -| XXXX X XX XXXX XXXXX XX XXXX XX XX XX -| XX X XXX XX XX X XX XX XX XXX XXXXXX XX -| XX X XX XX XX XX X XX XX XX XX XX XX XX XX -| XXXXXXX XXX XXX XXXX XXXXXXX XXX XX XX XX XX XX XXXXXXX -+*****************************************************************************/ -/****************************************************************************** -| -| Routine: INITB_EBIU0. -| -| Purpose: Initialize all the EBIU0 Bank Registers -| Parameters: None. -| Returns: None. -| -******************************************************************************/ - function_prolog(initb_ebiu0) - /*--------------------------------------------------------------------+ - | Set EBIU0 Bank 0 - +--------------------------------------------------------------------*/ - lis r10,EBIU0_BRCR0_VAL@h - ori r10,r10,EBIU0_BRCR0_VAL@l - mtdcr ebiu0_brcr0,r10 - lis r10,EBIU0_BRCRH0_VAL@h - ori r10,r10,EBIU0_BRCRH0_VAL@l - mtdcr ebiu0_brcrh0,r10 - - /*--------------------------------------------------------------------+ - | Set EBIU0 Bank 1 - +--------------------------------------------------------------------*/ - lis r10,EBIU0_BRCR1_VAL@h - ori r10,r10,EBIU0_BRCR1_VAL@l - mtdcr ebiu0_brcr1,r10 - lis r10,EBIU0_BRCRH1_VAL@h - ori r10,r10,EBIU0_BRCRH1_VAL@l - mtdcr ebiu0_brcrh1,r10 - - /*--------------------------------------------------------------------+ - | Set EBIU0 Bank 2 - +--------------------------------------------------------------------*/ - lis r10,EBIU0_BRCR2_VAL@h - ori r10,r10,EBIU0_BRCR2_VAL@l - mtdcr ebiu0_brcr2,r10 - lis r10,EBIU0_BRCRH2_VAL@h - ori r10,r10,EBIU0_BRCRH2_VAL@l - mtdcr ebiu0_brcrh2,r10 - - /*--------------------------------------------------------------------+ - | Set EBIU0 Bank 3 - +--------------------------------------------------------------------*/ - lis r10,EBIU0_BRCR3_VAL@h - ori r10,r10,EBIU0_BRCR3_VAL@l - mtdcr ebiu0_brcr3,r10 - lis r10,EBIU0_BRCRH3_VAL@h - ori r10,r10,EBIU0_BRCRH3_VAL@l - mtdcr ebiu0_brcrh3,r10 - - /*--------------------------------------------------------------------+ - | Set EBIU0 Bank 4 - +--------------------------------------------------------------------*/ - lis r10,EBIU0_BRCR4_VAL@h - ori r10,r10,EBIU0_BRCR4_VAL@l - mtdcr ebiu0_brcr4,r10 - lis r10,EBIU0_BRCRH4_VAL@h - ori r10,r10,EBIU0_BRCRH4_VAL@l - mtdcr ebiu0_brcrh4,r10 - - /*--------------------------------------------------------------------+ - | Set EBIU0 Bank 5 - +--------------------------------------------------------------------*/ - lis r10,EBIU0_BRCR5_VAL@h - ori r10,r10,EBIU0_BRCR5_VAL@l - mtdcr ebiu0_brcr5,r10 - lis r10,EBIU0_BRCRH5_VAL@h - ori r10,r10,EBIU0_BRCRH5_VAL@l - mtdcr ebiu0_brcrh5,r10 - - /*--------------------------------------------------------------------+ - | Set EBIU0 Bank 6 - +--------------------------------------------------------------------*/ - lis r10,EBIU0_BRCR6_VAL@h - ori r10,r10,EBIU0_BRCR6_VAL@l - mtdcr ebiu0_brcr6,r10 - lis r10,EBIU0_BRCRH6_VAL@h - ori r10,r10,EBIU0_BRCRH6_VAL@l - mtdcr ebiu0_brcrh6,r10 - - /*--------------------------------------------------------------------+ - | Set EBIU0 Bank 7 - +--------------------------------------------------------------------*/ - lis r10,EBIU0_BRCR7_VAL@h - ori r10,r10,EBIU0_BRCR7_VAL@l - mtdcr ebiu0_brcr7,r10 - lis r10,EBIU0_BRCRH7_VAL@h - ori r10,r10,EBIU0_BRCRH7_VAL@l - mtdcr ebiu0_brcrh7,r10 - - blr - function_epilog(initb_ebiu0) - - -/****************************************************************************** -| -| Routine: INITB_CONFIG -| -| Purpose: Configure the Vesta Evaluation Board. The following items -| will be configured: -| 1. Cross-Bar Switch. -| 2. Chip Interconnect. -| 3. Clear/reset key PPC registers. -| 4. Xilinx and GPIO Registers. -| -| Returns: None. -| -******************************************************************************/ - function_prolog(initb_config) - /*--------------------------------------------------------------------+ - | Init CROSS-BAR SWITCH - +--------------------------------------------------------------------*/ - lis r10,CBS0_CR_VAL@h /* r10 <- CBS Cntl Reg val */ - ori r10,r10,CBS0_CR_VAL@l - mtdcr cbs0_cr,r10 - - /*--------------------------------------------------------------------+ - | Init Chip-Interconnect (CIC) Registers - +--------------------------------------------------------------------*/ - lis r10,CIC0_CR_VAL@h /* r10 <- CIC Cntl Reg val */ - ori r10,r10,CIC0_CR_VAL@l - mtdcr cic0_cr,r10 - - lis r10,CIC0_SEL3_VAL@h /* r10 <- CIC SEL3 Reg val */ - ori r10,r10,CIC0_SEL3_VAL@l - mtdcr cic0_sel3,r10 - - lis r10,CIC0_VCR_VAL@h /* r10 <- CIC Vid C-Reg val */ - ori r10,r10,CIC0_VCR_VAL@l - mtdcr cic0_vcr,r10 - - /*--------------------------------------------------------------------+ - | Clear SGR and DCWR - +--------------------------------------------------------------------*/ - li r10,0x0000 - mtspr sgr,r10 - mtspr dcwr,r10 - - /*--------------------------------------------------------------------+ - | Clear/set up some machine state registers. - +--------------------------------------------------------------------*/ - li r10,0x0000 /* r10 <- 0 */ - mtdcr ebiu0_besr,r10 /* clr Bus Err Syndrome Reg */ - mtspr esr,r10 /* clr Exceptn Syndrome Reg */ - mttcr r10 /* timer control register */ - - mtdcr uic0_er,r10 /* disable all interrupts */ - - /* UIC_IIC0 | UIC_IIC1 | UIC_U0 | UIC_IR_RCV | UIC_IR_XMIT */ - lis r10, 0x00600e00@h - ori r10,r10,0x00600e00@l - mtdcr uic0_pr,r10 - - li r10,0x00000020 /* UIC_EIR1 */ - mtdcr uic0_tr,r10 - - lis r10,0xFFFF /* r10 <- 0xFFFFFFFF */ - ori r10,r10,0xFFFF /* */ - mtdbsr r10 /* clear/reset the dbsr */ - mtdcr uic0_sr,r10 /* clear pending interrupts */ - - li r10,0x1000 /* set Machine Exception bit*/ - oris r10,r10,0x2 /* set Criticl Exception bit*/ - mtmsr r10 /* change MSR */ - - /*--------------------------------------------------------------------+ - | Clear XER. - +--------------------------------------------------------------------*/ - li r10,0x0000 - mtxer r10 - - /*--------------------------------------------------------------------+ - | Init GPIO0 Registers - +--------------------------------------------------------------------*/ - lis r10, STB_GPIO0_TC@h /* Three-state control */ - ori r10,r10,STB_GPIO0_TC@l - lis r11, GPIO0_TC_VAL@h - ori r11,r11,GPIO0_TC_VAL@l - stw r11,0(r10) - - lis r10, STB_GPIO0_OS_0_31@h /* output select 0-31 */ - ori r10,r10,STB_GPIO0_OS_0_31@l - lis r11, GPIO0_OS_0_31_VAL@h - ori r11,r11,GPIO0_OS_0_31_VAL@l - stw r11,0(r10) - - lis r10, STB_GPIO0_OS_32_63@h /* output select 32-63 */ - ori r10,r10,STB_GPIO0_OS_32_63@l - lis r11, GPIO0_OS_32_63_VAL@h - ori r11,r11,GPIO0_OS_32_63_VAL@l - stw r11,0(r10) - - lis r10, STB_GPIO0_TS_0_31@h /* three-state select 0-31 */ - ori r10,r10,STB_GPIO0_TS_0_31@l - lis r11, GPIO0_TS_0_31_VAL@h - ori r11,r11,GPIO0_TS_0_31_VAL@l - stw r11,0(r10) - - lis r10, STB_GPIO0_TS_32_63@h /* three-state select 32-63 */ - ori r10,r10,STB_GPIO0_TS_32_63@l - lis r11, GPIO0_TS_32_63_VAL@h - ori r11,r11,GPIO0_TS_32_63_VAL@l - stw r11,0(r10) - - lis r10, STB_GPIO0_OD@h /* open drain */ - ori r10,r10,STB_GPIO0_OD@l - lis r11, GPIO0_OD_VAL@h - ori r11,r11,GPIO0_OD_VAL@l - stw r11,0(r10) - - lis r10, STB_GPIO0_IS_1_0_31@h /* input select 1, 0-31 */ - ori r10,r10,STB_GPIO0_IS_1_0_31@l - lis r11, GPIO0_IS_1_0_31_VAL@h - ori r11,r11,GPIO0_IS_1_0_31_VAL@l - stw r11,0(r10) - - lis r10, STB_GPIO0_IS_1_32_63@h /* input select 1, 32-63 */ - ori r10,r10,STB_GPIO0_IS_1_32_63@l - lis r11, GPIO0_IS_1_32_63_VAL@h - ori r11,r11,GPIO0_IS_1_32_63_VAL@l - stw r11,0(r10) - - lis r10, STB_GPIO0_IS_2_0_31@h /* input select 2, 0-31 */ - ori r10,r10,STB_GPIO0_IS_2_0_31@l - lis r11, GPIO0_IS_2_0_31_VAL@h - ori r11,r11,GPIO0_IS_2_0_31_VAL@l - stw r11,0(r10) - - lis r10, STB_GPIO0_IS_2_32_63@h /* input select 2, 32-63 */ - ori r10,r10,STB_GPIO0_IS_2_32_63@l - lis r11, GPIO0_IS_2_32_63_VAL@h - ori r11,r11,GPIO0_IS_2_32_63_VAL@l - stw r11,0(r10) - - lis r10, STB_GPIO0_IS_3_0_31@h /* input select 3, 0-31 */ - ori r10,r10,STB_GPIO0_IS_3_0_31@l - lis r11, GPIO0_IS_3_0_31_VAL@h - ori r11,r11,GPIO0_IS_3_0_31_VAL@l - stw r11,0(r10) - - lis r10, STB_GPIO0_IS_3_32_63@h /* input select 3, 32-63 */ - ori r10,r10,STB_GPIO0_IS_3_32_63@l - lis r11, GPIO0_IS_3_32_63_VAL@h - ori r11,r11,GPIO0_IS_3_32_63_VAL@l - stw r11,0(r10) - - lis r10, STB_GPIO0_SS_1@h /* sync select 1 */ - ori r10,r10,STB_GPIO0_SS_1@l - lis r11, GPIO0_SS_1_VAL@h - ori r11,r11,GPIO0_SS_1_VAL@l - stw r11,0(r10) - - lis r10, STB_GPIO0_SS_2@h /* sync select 2 */ - ori r10,r10,STB_GPIO0_SS_2@l - lis r11, GPIO0_SS_2_VAL@h - ori r11,r11,GPIO0_SS_2_VAL@l - stw r11,0(r10) - - lis r10, STB_GPIO0_SS_3@h /* sync select 3 */ - ori r10,r10,STB_GPIO0_SS_3@l - lis r11, GPIO0_SS_3_VAL@h - ori r11,r11,GPIO0_SS_3_VAL@l - stw r11,0(r10) - - /*--------------------------------------------------------------------+ - | Init Xilinx #1 Registers - +--------------------------------------------------------------------*/ - lis r10, STB_XILINX1_REG0@h /* init Xilinx1 Reg 0 */ - ori r10,r10,STB_XILINX1_REG0@l - li r11,XILINX1_R0_VAL - sth r11,0(r10) - - lis r10, STB_XILINX1_REG1@h /* init Xilinx1 Reg 1 */ - ori r10,r10,STB_XILINX1_REG1@l - li r11,XILINX1_R1_VAL - sth r11,0(r10) - - lis r10, STB_XILINX1_REG2@h /* init Xilinx1 Reg 2 */ - ori r10,r10,STB_XILINX1_REG2@l - li r11,XILINX1_R2_VAL - sth r11,0(r10) - - lis r10, STB_XILINX1_REG3@h /* init Xilinx1 Reg 3 */ - ori r10,r10,STB_XILINX1_REG3@l - li r11,XILINX1_R3_VAL - sth r11,0(r10) - - lis r10, STB_XILINX1_REG4@h /* init Xilinx1 Reg 4 */ - ori r10,r10,STB_XILINX1_REG4@l - li r11,XILINX1_R4_VAL - sth r11,0(r10) - - lis r10, STB_XILINX1_REG5@h /* init Xilinx1 Reg 5 */ - ori r10,r10,STB_XILINX1_REG5@l - li r11,XILINX1_R5_VAL - sth r11,0(r10) - - lis r10, STB_XILINX1_REG6@h /* init Xilinx1 Reg 6 */ - ori r10,r10,STB_XILINX1_REG6@l - li r11,XILINX1_R6_VAL - sth r11,0(r10) - - lis r10, STB_XILINX1_FLUSH@h /* latch registers in Xilinx*/ - ori r10,r10,STB_XILINX1_FLUSH@l - li r11,0x0000 - sth r11,0(r10) - - /*--------------------------------------------------------------------+ - | Init Xilinx #2 Registers - +--------------------------------------------------------------------*/ - lis r10, STB_XILINX2_REG0@h /* init Xilinx2 Reg 0 */ - ori r10,r10,STB_XILINX2_REG0@l - li r11,XILINX2_R0_VAL - sth r11,0(r10) - - lis r10, STB_XILINX2_REG1@h /* init Xilinx2 Reg 1 */ - ori r10,r10,STB_XILINX2_REG1@l - li r11,XILINX2_R1_VAL - sth r11,0(r10) - - lis r10, STB_XILINX2_REG2@h /* init Xilinx2 Reg 2 */ - ori r10,r10,STB_XILINX2_REG2@l - li r11,XILINX2_R2_VAL - sth r11,0(r10) - - blr - function_epilog(initb_config) - - -/****************************************************************************** -| -| Routine: INITB_HSMC0. -| -| Purpose: Initialize the HSMC0 Registers for SDRAM -| Parameters: None. -| Returns: R3 = 0: Successful -| = -1: Unsuccessful, SDRAM did not reset properly. -| -******************************************************************************/ - function_prolog(initb_hsmc0) - mflr r0 /* Save return addr */ - - /*--------------------------------------------------------------------+ - | Set Global SDRAM Controller to recommended default - +--------------------------------------------------------------------*/ - lis r10,0x6C00 - ori r10,r10,0x0000 - mtdcr hsmc0_gr,r10 - - /*--------------------------------------------------------------------+ - | Set HSMC0 Data Register to recommended default - +--------------------------------------------------------------------*/ - lis r10,0x0037 - ori r10,r10,0x0000 - mtdcr hsmc0_data,r10 - - /*--------------------------------------------------------------------+ - | Init HSMC0 Bank Register 0 - +--------------------------------------------------------------------*/ - lis r10,HSMC0_BR0_VAL@h - ori r10,r10,HSMC0_BR0_VAL@l - mtdcr hsmc0_br0,r10 - - /*--------------------------------------------------------------------+ - | Init HSMC0 Bank Register 1 - +--------------------------------------------------------------------*/ - lis r10,HSMC0_BR1_VAL@h - ori r10,r10,HSMC0_BR1_VAL@l - mtdcr hsmc0_br1,r10 - - /*--------------------------------------------------------------------+ - | Set HSMC0 Control Reg 0 - +--------------------------------------------------------------------*/ - lis r10,0x8077 /* PRECHARGE ALL DEVICE BKS */ - ori r10,r10,0x0000 - mtdcr hsmc0_cr0,r10 - li r3,0x0000 - bl hsmc_cr_wait /* wait for op completion */ - cmpwi cr0,r3,0x0000 - bne cr0,hsmc0_err - - lis r10,0x8078 /* AUTO-REFRESH */ - ori r10,r10,0x0000 - mtdcr hsmc0_cr0,r10 - li r3,0x0000 - bl hsmc_cr_wait /* wait for op completion */ - cmpwi cr0,r3,0x0000 - bne cr0,hsmc0_err - - lis r10,0x8070 /* PROG MODE W/DATA REG VAL */ - ori r10,r10,0x8000 - mtdcr hsmc0_cr0,r10 - li r3,0x0000 - bl hsmc_cr_wait /* wait for op completion */ - cmpwi cr0,r3,0x0000 - bne hsmc0_err - - /*--------------------------------------------------------------------+ - | Set HSMC0 Control Reg 1 - +--------------------------------------------------------------------*/ - lis r10,0x8077 /* PRECHARGE ALL DEVICE BKS */ - ori r10,r10,0x0000 - mtdcr hsmc0_cr1,r10 - li r3,0x0001 - bl hsmc_cr_wait /* wait for op completion */ - cmpwi cr0,r3,0x0000 - bne cr0,hsmc0_err - - lis r10,0x8078 /* AUTO-REFRESH */ - ori r10,r10,0x0000 - mtdcr hsmc0_cr1,r10 - li r3,0x0001 - bl hsmc_cr_wait /* wait for op completion */ - cmpwi cr0,r3,0x0000 - bne cr0,hsmc0_err - - lis r10,0x8070 /* PROG MODE W/DATA REG VAL */ - ori r10,r10,0x8000 - mtdcr hsmc0_cr1,r10 - li r3,0x0001 - bl hsmc_cr_wait /* wait for op completion */ - cmpwi cr0,r3,0x0000 - bne cr0,hsmc0_err - - /*--------------------------------------------------------------------+ - | Set HSMC0 Refresh Register - +--------------------------------------------------------------------*/ - lis r10,0x0FE1 - ori r10,r10,0x0000 - mtdcr hsmc0_crr,r10 - li r3,0 - -hsmc0_err: - mtlr r0 - blr - function_epilog(initb_hsmc0) - - -/****************************************************************************** -| -| Routine: INITB_HSMC1. -| -| Purpose: Initialize the HSMC1 Registers for SDRAM -| Parameters: None. -| Returns: R3 = 0: Successful -| = -1: Unsuccessful, SDRAM did not reset properly. -| -******************************************************************************/ - function_prolog(initb_hsmc1) - mflr r0 /* Save return addr */ - - /*--------------------------------------------------------------------+ - | Set Global SDRAM Controller to recommended default - +--------------------------------------------------------------------*/ - lis r10,0x6C00 - ori r10,r10,0x0000 - mtdcr hsmc1_gr,r10 - - /*--------------------------------------------------------------------+ - | Set HSMC1 Data Register to recommended default - +--------------------------------------------------------------------*/ - lis r10,0x0037 - ori r10,r10,0x0000 - mtdcr hsmc1_data,r10 - - /*--------------------------------------------------------------------+ - | Init HSMC1 Bank Register 0 - +--------------------------------------------------------------------*/ - lis r10,HSMC1_BR0_VAL@h - ori r10,r10,HSMC1_BR0_VAL@l - mtdcr hsmc1_br0,r10 - - /*--------------------------------------------------------------------+ - | Init HSMC1 Bank Register 1 - +--------------------------------------------------------------------*/ - lis r10,HSMC1_BR1_VAL@h - ori r10,r10,HSMC1_BR1_VAL@l - mtdcr hsmc1_br1,r10 - - /*--------------------------------------------------------------------+ - | Set HSMC1 Control Reg 0 - +--------------------------------------------------------------------*/ - lis r10,0x8077 /* PRECHARGE ALL DEVICE BANKS */ - ori r10,r10,0x0000 - mtdcr hsmc1_cr0,r10 - li r3,0x0002 - bl hsmc_cr_wait /* wait for operation completion */ - cmpwi cr0,r3,0x0000 - bne hsmc1_err - - lis r10,0x8078 /* AUTO-REFRESH */ - ori r10,r10,0x0000 - mtdcr hsmc1_cr0,r10 - li r3,0x0002 - bl hsmc_cr_wait /* wait for operation completion */ - cmpwi cr0,r3,0x0000 - bne hsmc1_err - - lis r10,0x8070 /* PROGRAM MODE W/DATA REG VALUE */ - ori r10,r10,0x8000 - mtdcr hsmc1_cr0,r10 - li r3,0x0002 - bl hsmc_cr_wait /* wait for operation completion */ - cmpwi cr0,r3,0x0000 - bne hsmc1_err - - /*--------------------------------------------------------------------+ - | Set HSMC1 Control Reg 1 - +--------------------------------------------------------------------*/ - lis r10,0x8077 /* PRECHARGE ALL DEVICE BKS */ - ori r10,r10,0x0000 - mtdcr hsmc1_cr1,r10 - li r3,0x0003 - bl hsmc_cr_wait /* wait for op completion */ - cmpwi cr0,r3,0x0000 - bne hsmc1_err - - lis r10,0x8078 /* AUTO-REFRESH */ - ori r10,r10,0x0000 - mtdcr hsmc1_cr1,r10 - li r3,0x0003 - bl hsmc_cr_wait /* wait for op completion */ - cmpwi cr0,r3,0x0000 - bne hsmc1_err - - lis r10,0x8070 /* PROG MODE W/DATA REG VAL */ - ori r10,r10,0x8000 - mtdcr hsmc1_cr1,r10 - li r3,0x0003 - bl hsmc_cr_wait /* wait for op completion */ - cmpwi cr0,r3,0x0000 - bne hsmc1_err - - /*--------------------------------------------------------------------+ - | Set HSMC1 Refresh Register - +--------------------------------------------------------------------*/ - lis r10,0x0FE1 - ori r10,r10,0x0000 - mtdcr hsmc1_crr,r10 - xor r3,r3,r3 - -hsmc1_err: - mtlr r0 - blr - function_epilog(initb_hsmc1) - - -/****************************************************************************** -| -| Routine: INITB_CACHE -| -| Purpose: This routine will enable Data and Instruction Cache. -| The Data Cache is an 8K two-way set associative and the -| Instruction Cache is an 16K two-way set associative cache. -| -| Parameters: None. -| -| Returns: None. -| -******************************************************************************/ - function_prolog(initb_cache) - mflr r0 /* Save return addr */ - - bl initb_Dcache /* enable D-Cache */ - bl initb_Icache /* enable I-Cache */ - - mtlr r0 - blr - function_epilog(initb_cache) - - -/****************************************************************************** -| -| Routine: INITB_DCACHE -| -| Purpose: This routine will invalidate all data in the Data Cache and -| then enable D-Cache. If cache is enabled already, the D-Cache -| will be flushed before the data is invalidated. -| -| Parameters: None. -| -| Returns: None. -| -******************************************************************************/ - function_prolog(initb_Dcache) - /*--------------------------------------------------------------------+ - | Flush Data Cache if enabled - +--------------------------------------------------------------------*/ - mfdccr r10 /* r10 <- DCCR */ - isync /* ensure prev insts done */ - cmpwi r10,0x00 - beq ic_dcinv /* D-cache off, invalidate */ - - /*--------------------------------------------------------------------+ - | Data Cache enabled, force known memory addresses to be Cached - +--------------------------------------------------------------------*/ - lis r10,HSMC0_BR0_VAL@h /* r10 <- first memory loc */ - andis. r10,r10,0xFFF0 - li r11,DCACHE_NLINES /* r11 <- # A-way addresses */ - addi r11,r11,DCACHE_NLINES /* r11 <- # B-way addresses */ - mtctr r11 /* set loop counter */ - -ic_dcload: - lwz r12,0(r10) /* force cache of address */ - addi r10,r10,DCACHE_NBYTES /* r10 <- next memory loc */ - bdnz ic_dcload - sync /* ensure prev insts done */ - isync - - /*--------------------------------------------------------------------+ - | Flush the known memory addresses from Cache - +--------------------------------------------------------------------*/ - lis r10,HSMC0_BR0_VAL@h /* r10 <- first memory loc */ - andis. r10,r10,0xFFF0 - mtctr r11 /* set loop counter */ - -ic_dcflush: - dcbf 0,r10 /* flush D-cache line */ - addi r10,r10,DCACHE_NBYTES /* r10 <- next memory loc */ - bdnz ic_dcflush - sync /* ensure prev insts done */ - isync - - /*--------------------------------------------------------------------+ - | Disable then invalidate Data Cache - +--------------------------------------------------------------------*/ - li r10,0 /* r10 <- 0 */ - mtdccr r10 /* disable the D-Cache */ - isync /* ensure prev insts done */ - -ic_dcinv: - li r10,0 /* r10 <- line address */ - li r11,DCACHE_NLINES /* r11 <- # lines in cache */ - mtctr r11 /* set loop counter */ - -ic_dcloop: - dccci 0,r10 /* invalidate A/B cache lns */ - addi r10,r10,DCACHE_NBYTES /* bump to next line */ - bdnz ic_dcloop - sync /* ensure prev insts done */ - isync - - /*--------------------------------------------------------------------+ - | Enable Data Cache - +--------------------------------------------------------------------*/ - lis r10,DCACHE_ENABLE@h /* r10 <- D-cache enable msk*/ - ori r10,r10,DCACHE_ENABLE@l - mtdccr r10 - sync /* ensure prev insts done */ - isync - - blr - function_epilog(initb_Dcache) - - -/****************************************************************************** -| -| Routine: INITB_ICACHE -| -| Purpose: This routine will invalidate all data in the Instruction -| Cache then enable I-Cache. -| -| Parameters: None. -| -| Returns: None. -| -******************************************************************************/ - function_prolog(initb_Icache) - /*--------------------------------------------------------------------+ - | Invalidate Instruction Cache - +--------------------------------------------------------------------*/ - li r10,0 /* r10 <- lines address */ - iccci 0,r10 /* invalidate all I-cache */ - sync /* ensure prev insts done */ - isync - - /*--------------------------------------------------------------------+ - | Enable Instruction Cache - +--------------------------------------------------------------------*/ - lis r10,ICACHE_ENABLE@h /* r10 <- I-cache enable msk*/ - ori r10,r10,ICACHE_ENABLE@l - mticcr r10 - sync /* ensure prev insts done */ - isync - - blr - function_epilog(initb_Icache) - -#if 0 -/****************************************************************************** -| -| Routine: INITB_GET_CSPD -| -| Purpose: Determine the CPU Core Speed. The 13.5 Mhz Time Base -| Counter (TBC) is used to measure a conditional branch -| instruction. -| -| Parameters: R3 = Address of Bus Speed -| R4 = Address of Core Speed -| -| Returns: (R3) = >0: Bus Speed. -| 0: Bus Speed not found in Look-Up Table. -| (R4) = >0: Core Speed. -| 0: Core Speed not found in Look-Up Table. -| -| Note: 1. This routine assumes the bdnz branch instruction takes -| two instruction cycles to complete. -| 2. This routine must be called before interrupts are enabled. -| -******************************************************************************/ - function_prolog(initb_get_cspd) - mflr r0 /* Save return address */ - /*--------------------------------------------------------------------+ - | Set-up timed loop - +--------------------------------------------------------------------*/ - lis r9,gcs_time_loop@h /* r9 <- addr loop instr */ - ori r9,r9,gcs_time_loop@l - lis r10,GCS_LCNT@h /* r10 <- loop count */ - ori r10,r10,GCS_LCNT@l - mtctr r10 /* ctr <- loop count */ - lis r11,STB_TIMERS_TBC@h /* r11 <- TBC register addr */ - ori r11,r11,STB_TIMERS_TBC@l - li r12,0 /* r12 <- 0 */ - - /*--------------------------------------------------------------------+ - | Cache timed-loop instruction - +--------------------------------------------------------------------*/ - icbt 0,r9 - sync - isync - - /*--------------------------------------------------------------------+ - | Get number of 13.5 Mhz cycles to execute time-loop - +--------------------------------------------------------------------*/ - stw r12,0(r11) /* reset TBC */ -gcs_time_loop: - bdnz+ gcs_time_loop /* force branch pred taken */ - lwz r5,0(r11) /* r5 <- num 13.5 Mhz ticks */ - li r6,5 /* LUT based on 1/5th the...*/ - divw r5,r5,r6 /*..loop count used */ - sync - isync - - /*--------------------------------------------------------------------+ - | Look-up core speed based on TBC value - +--------------------------------------------------------------------*/ - lis r6,gcs_lookup_table@h /* r6 <- pts at core spd LUT*/ - ori r6,r6,gcs_lookup_table@l - bl gcs_cspd_lookup /* find core speed in LUT */ - - mtlr r0 /* set return address */ - blr - function_epilog(initb_get_cspd) - -#endif -/*****************************************************************************+ -| XXXX XX XX XXXXXX XXXXXXX XXXXXX XX XX XX XXXX -| XX XXX XX X XX X XX X XX XX XXX XX XXXX XX -| XX XXXX XX XX XX X XX XX XXXX XX XX XX XX -| XX XX XXXX XX XXXX XXXXX XX XXXX XX XX XX -| XX XX XXX XX XX X XX XX XX XXX XXXXXX XX -| XX XX XX XX XX X XX XX XX XX XX XX XX XX -| XXXX XX XX XXXX XXXXXXX XXX XX XX XX XX XX XXXXXXX -+*****************************************************************************/ -/****************************************************************************** -| -| Routine: HSMC_CR_WAIT -| -| Purpose: Wait for the HSMC Control Register (bits 12-16) to be reset -| after an auto-refresh, pre-charge or program mode register -| command execution. -| -| Parameters: R3 = HSMC Control Register ID. -| 0: HSMC0 CR0 -| 1: HSMC0 CR1 -| 2: HSMC1 CR0 -| 3: HSMC1 CR1 -| -| Returns: R3 = 0: Successful -| -1: Unsuccessful -| -******************************************************************************/ -hsmc_cr_wait: - - li r11,10 /* r11 <- retry counter */ - mtctr r11 /* set retry counter */ - mr r11,r3 /* r11 <- HSMC CR reg id */ - -hsmc_cr_rep: - bdz hsmc_cr_err /* branch if max retries hit*/ - - /*--------------------------------------------------------------------+ - | GET HSMCx_CRx value based on HSMC Control Register ID - +--------------------------------------------------------------------*/ -try_hsmc0_cr0: /* CHECK IF ID=HSMC0 CR0 REG*/ - cmpwi cr0,r11,0x0000 - bne cr0,try_hsmc0_cr1 - mfdcr r10,hsmc0_cr0 /* r11 <- HSMC0 CR0 value */ - b hsmc_cr_read - -try_hsmc0_cr1: /* CHECK IF ID=HSMC0 CR1 REG*/ - cmpwi cr0,r11,0x0001 - bne cr0,try_hsmc1_cr0 - mfdcr r10,hsmc0_cr1 /* r10 <- HSMC0 CR1 value */ - b hsmc_cr_read - -try_hsmc1_cr0: /* CHECK IF ID=HSMC1 CR0 REG*/ - cmpwi cr0,r11,0x0002 - bne cr0,try_hsmc1_cr1 - mfdcr r10,hsmc1_cr0 /* r10 <- HSMC1 CR0 value */ - b hsmc_cr_read - -try_hsmc1_cr1: /* CHECK IF ID=HSMC1 CR1 REG*/ - cmpwi cr0,r11,0x0003 - bne cr0,hsmc_cr_err - mfdcr r10,hsmc1_cr1 /* r10 <- HSMC1 CR1 value */ - - /*--------------------------------------------------------------------+ - | Check if HSMC CR register was reset after command execution - +--------------------------------------------------------------------*/ -hsmc_cr_read: - lis r12,0x000F /* create "AND" mask */ - ori r12,r12,0x8000 - and. r10,r10,r12 /* r10 <- HSMC CR bits 12-16*/ - bne cr0,hsmc_cr_rep /* wait for bits to reset */ - li r3,0 /* set return code = success*/ - b hsmc_cr_done - -hsmc_cr_err: /* ERROR: SDRAM didn't reset*/ - li r3,-1 /* set RC=unsuccessful */ - -hsmc_cr_done: - blr - -#if 0 -/****************************************************************************** -| -| Routine: GCS_CSPD_LOOKUP -| -| Purpose: Uses the number of 13.5 Mhz clock ticks found after executing -| the branch instruction time loop to look-up the CPU Core Speed -| in the Core Speed Look-up Table. -| -| Parameters: R3 = Address of Bus Speed -| R4 = Address of Core Speed -| R5 = Number of 13.5 Mhz clock ticks found in time loop. -| R6 = Pointer to Core-Speed Look-Up Table -| -| Returns: (R3) = >0: Bus Speed. -| 0: Bus Speed not found in Look-Up Table. -| (R4) = >0: Core Speed. -| 0: Core Speed not found in Look-Up Table. -| -| Note: Core Speed = Bus Speed * Mult Factor (1-4x). -| -******************************************************************************/ -gcs_cspd_lookup: - - li r9,1 /* r9 <- core speed mult */ - /*--------------------------------------------------------------------+ - | Get theoritical number 13.5 Mhz ticks for a given Bus Speed from - | Look-up Table. Check all mult factors to determine if calculated - | value matches theoretical value (within a tolerance). - +--------------------------------------------------------------------*/ -gcs_cspd_loop: - lwz r10,0(r6) /* r10 <- no. ticks from LUT*/ - divw r10,r10,r9 /* r10 <- div mult (1-4x) */ - subi r11,r10,GCS_CTICK_TOL /* r11 <- no. tks low range */ - addi r12,r10,GCS_CTICK_TOL /* r12 <- no. tks high range*/ - - cmpw cr0,r5,r11 /* calc value within range? */ - blt gcs_cspd_retry /* less than low range */ - cmpw cr0,r5,r12 - bgt gcs_cspd_retry /* greater than high range */ - b gcs_cspd_fnd /* calc value within range */ - - /*--------------------------------------------------------------------+ - | SO FAR CORE SPEED NOT FOUND: Check next mult factor - +--------------------------------------------------------------------*/ -gcs_cspd_retry: - addi r9,r9,1 /* bump mult factor (1-4x) */ - cmpwi cr0,r9,GCS_NMULT - ble gcs_cspd_loop - - /*--------------------------------------------------------------------+ - | SO FAR CORE SPEED NOT FOUND: Point at next Bus Speed in LUT - +--------------------------------------------------------------------*/ - li r9,1 /* reset mult factor */ - addi r6,r6,GCS_TROW_BYTES /* point at next table entry*/ - lwz r10,0(r6) - cmpwi cr0,r10,0 /* check for EOT flag */ - bne gcs_cspd_loop - - /*--------------------------------------------------------------------+ - | COMPUTE CORE SPEED AND GET BUS SPEED FROM LOOK-UP TABLE - +--------------------------------------------------------------------*/ -gcs_cspd_fnd: - lwz r5,4(r6) /* r5 <- Bus Speed in LUT */ - mullw r6,r5,r9 /* r6 <- Core speed */ - stw r5,0(r3) /* (r3) <- Bus Speed */ - stw r6,0(r4) /* (r4) <- Core Speed */ - - blr -#endif diff --git a/arch/ppc/boot/simple/rw4/stb.h b/arch/ppc/boot/simple/rw4/stb.h deleted file mode 100644 index 9afa5ab24d26..000000000000 --- a/arch/ppc/boot/simple/rw4/stb.h +++ /dev/null @@ -1,239 +0,0 @@ -/*----------------------------------------------------------------------------+ -| This source code has been made available to you by IBM on an AS-IS -| basis. Anyone receiving this source is licensed under IBM -| copyrights to use it in any way he or she deems fit, including -| copying it, modifying it, compiling it, and redistributing it either -| with or without modifications. No license under IBM patents or -| patent applications is to be implied by the copyright license. -| -| Any user of this software should understand that IBM cannot provide -| technical support for this software and will not be responsible for -| any consequences resulting from the use of this software. -| -| Any person who transfers this source code or any derivative work -| must include the IBM copyright notice, this paragraph, and the -| preceding two paragraphs in the transferred software. -| -| COPYRIGHT I B M CORPORATION 1999 -| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M -+----------------------------------------------------------------------------*/ -/*----------------------------------------------------------------------------+ -| Author: Maciej P. Tyrlik -| Component: Include file. -| File: stb.h -| Purpose: Common Set-tob-box definitions. -| Changes: -| Date: Comment: -| ----- -------- -| 14-Jan-97 Created for ElPaso pass 1 MPT -| 13-May-97 Added function prototype and global variables MPT -| 08-Dec-98 Added RAW IR task information MPT -| 19-Jan-99 Port to Romeo MPT -| 19-May-00 Changed SDRAM to 32MB contiguous 0x1F000000 - 0x20FFFFFF RLB -+----------------------------------------------------------------------------*/ - -#ifndef _stb_h_ -#define _stb_h_ - -/*----------------------------------------------------------------------------+ -| Read/write from I/O macros. -+----------------------------------------------------------------------------*/ -#define inbyte(port) (*((unsigned char volatile *)(port))) -#define outbyte(port,data) *(unsigned char volatile *)(port)=\ - (unsigned char)(data) - -#define inshort(port) (*((unsigned short volatile *)(port))) -#define outshort(port,data) *(unsigned short volatile *)(port)=\ - (unsigned short)(data) - -#define inword(port) (*((unsigned long volatile *)(port))) -#define outword(port,data) *(unsigned long volatile *)(port)=\ - (unsigned long)(data) - -/*----------------------------------------------------------------------------+ -| STB interrupts. -+----------------------------------------------------------------------------*/ -#define STB_XP_TP_INT 0 -#define STB_XP_APP_INT 1 -#define STB_AUD_INT 2 -#define STB_VID_INT 3 -#define STB_DMA0_INT 4 -#define STB_DMA1_INT 5 -#define STB_DMA2_INT 6 -#define STB_DMA3_INT 7 -#define STB_SCI_INT 8 -#define STB_I2C1_INT 9 -#define STB_I2C2_INT 10 -#define STB_GPT_PWM0 11 -#define STB_GPT_PWM1 12 -#define STB_SCP_INT 13 -#define STB_SSP_INT 14 -#define STB_GPT_PWM2 15 -#define STB_EXT5_INT 16 -#define STB_EXT6_INT 17 -#define STB_EXT7_INT 18 -#define STB_EXT8_INT 19 -#define STB_SCC_INT 20 -#define STB_SICC_RECV_INT 21 -#define STB_SICC_TRAN_INT 22 -#define STB_PPU_INT 23 -#define STB_DCRX_INT 24 -#define STB_EXT0_INT 25 -#define STB_EXT1_INT 26 -#define STB_EXT2_INT 27 -#define STB_EXT3_INT 28 -#define STB_EXT4_INT 29 -#define STB_REDWOOD_ENET_INT STB_EXT1_INT - -/*----------------------------------------------------------------------------+ -| STB tasks, task stack sizes, and task priorities. The actual task priority -| is 1 more than the specified number since priority 0 is reserved (system -| internally adds 1 to supplied priority number). -+----------------------------------------------------------------------------*/ -#define STB_IDLE_TASK_SS (5* 1024) -#define STB_IDLE_TASK_PRIO 0 -#define STB_LEDTEST_SS (2* 1024) -#define STB_LEDTEST_PRIO 0 -#define STB_CURSOR_TASK_SS (10* 1024) -#define STB_CURSOR_TASK_PRIO 7 -#define STB_MPEG_TASK_SS (10* 1024) -#define STB_MPEG_TASK_PRIO 9 -#define STB_DEMUX_TASK_SS (10* 1024) -#define STB_DEMUX_TASK_PRIO 20 -#define RAW_STB_IR_TASK_SS (10* 1024) -#define RAW_STB_IR_TASK_PRIO 20 - -#define STB_SERIAL_ER_TASK_SS (10* 1024) -#define STB_SERIAL_ER_TASK_PRIO 1 -#define STB_CA_TASK_SS (10* 1024) -#define STB_CA_TASK_PRIO 8 - -#define INIT_DEFAULT_VIDEO_SS (10* 1024) -#define INIT_DEFAULT_VIDEO_PRIO 8 -#define INIT_DEFAULT_SERVI_SS (10* 1024) -#define INIT_DEFAULT_SERVI_PRIO 8 -#define INIT_DEFAULT_POST_SS (10* 1024) -#define INIT_DEFAULT_POST_PRIO 8 -#define INIT_DEFAULT_INTER_SS (10* 1024) -#define INIT_DEFAULT_INTER_PRIO 8 -#define INIT_DEFAULT_BR_SS (10* 1024) -#define INIT_DEFAULT_BR_PRIO 8 -#define INITIAL_TASK_STACK_SIZE (32* 1024) - -#ifdef VESTA -/*----------------------------------------------------------------------------+ -| Vesta Overall Address Map (all addresses are double mapped, bit 0 of the -| address is not decoded. Numbers below are dependent on board configuration. -| FLASH, SDRAM, DRAM numbers can be affected by actual board setup. -| -| FFE0,0000 - FFFF,FFFF FLASH -| F200,0000 - F210,FFFF FPGA logic -| Ethernet = F200,0000 -| LED Display = F200,0100 -| Xilinx #1 Regs = F204,0000 -| Xilinx #2 Regs = F208,0000 -| Spare = F20C,0000 -| IDE CS0 = F210,0000 -| F410,0000 - F410,FFFF IDE CS1 -| C000,0000 - C7FF,FFFF OBP -| C000,0000 - C000,0014 SICC (16550 + infra red) -| C001,0000 - C001,0018 PPU (Parallel Port) -| C002,0000 - C002,001B SC0 (Smart Card 0) -| C003,0000 - C003,000F I2C0 -| C004,0000 - C004,0009 SCC (16550 UART) -| C005,0000 - C005,0124 GPT (Timers) -| C006,0000 - C006,0058 GPIO0 -| C007,0000 - C007,001b SC1 (Smart Card 1) -| C008,0000 - C008,FFFF Unused -| C009,0000 - C009,FFFF Unused -| C00A,0000 - C00A,FFFF Unused -| C00B,0000 - C00B,000F I2C1 -| C00C,0000 - C00C,0006 SCP -| C00D,0000 - C00D,0010 SSP -| A000,0000 - A0FF,FFFF SDRAM1 (16M) -| 0000,0000 - 00FF,FFFF SDRAM0 (16M) -+----------------------------------------------------------------------------*/ -#define STB_FLASH_BASE_ADDRESS 0xFFE00000 -#define STB_FPGA_BASE_ADDRESS 0xF2000000 -#define STB_SICC_BASE_ADDRESS 0xC0000000 -#define STB_PPU_BASE_ADDR 0xC0010000 -#define STB_SC0_BASE_ADDRESS 0xC0020000 -#define STB_I2C1_BASE_ADDRESS 0xC0030000 -#define STB_SCC_BASE_ADDRESS 0xC0040000 -#define STB_TIMERS_BASE_ADDRESS 0xC0050000 -#define STB_GPIO0_BASE_ADDRESS 0xC0060000 -#define STB_SC1_BASE_ADDRESS 0xC0070000 -#define STB_I2C2_BASE_ADDRESS 0xC00B0000 -#define STB_SCP_BASE_ADDRESS 0xC00C0000 -#define STB_SSP_BASE_ADDRESS 0xC00D0000 -/*----------------------------------------------------------------------------+ -|The following are used by the IBM RTOS SW. -|15-May-00 Changed these values to reflect movement of base addresses in -|order to support 32MB of contiguous SDRAM space. -|Points to the cacheable region since these values are used in IBM RTOS -|to establish the vector address. -+----------------------------------------------------------------------------*/ -#define STB_SDRAM1_BASE_ADDRESS 0x20000000 -#define STB_SDRAM1_SIZE 0x01000000 -#define STB_SDRAM0_BASE_ADDRESS 0x1F000000 -#define STB_SDRAM0_SIZE 0x01000000 - -#else -/*----------------------------------------------------------------------------+ -| ElPaso Overall Address Map (all addresses are double mapped, bit 0 of the -| address is not decoded. Numbers below are dependent on board configuration. -| FLASH, SDRAM, DRAM numbers can be affected by actual board setup. OPB -| devices are inside the ElPaso chip. -| FFE0,0000 - FFFF,FFFF FLASH -| F144,0000 - F104,FFFF FPGA logic -| F140,0000 - F100,0000 ethernet (through FPGA logic) -| C000,0000 - C7FF,FFFF OBP -| C000,0000 - C000,0014 SICC (16550+ infra red) -| C001,0000 - C001,0016 PPU (parallel port) -| C002,0000 - C002,001B SC (smart card) -| C003,0000 - C003,000F I2C 1 -| C004,0000 - C004,0009 SCC (16550 UART) -| C005,0000 - C005,0124 Timers -| C006,0000 - C006,0058 GPIO0 -| C007,0000 - C007,0058 GPIO1 -| C008,0000 - C008,0058 GPIO2 -| C009,0000 - C009,0058 GPIO3 -| C00A,0000 - C00A,0058 GPIO4 -| C00B,0000 - C00B,000F I2C 2 -| C00C,0000 - C00C,0006 SCP -| C00D,0000 - C00D,0006 SSP -| A000,0000 - A0FF,FFFF SDRAM 16M -| 0000,0000 - 00FF,FFFF DRAM 16M -+----------------------------------------------------------------------------*/ -#define STB_FLASH_BASE_ADDRESS 0xFFE00000 -#define STB_FPGA_BASE_ADDRESS 0xF1440000 -#define STB_ENET_BASE_ADDRESS 0xF1400000 -#define STB_SICC_BASE_ADDRESS 0xC0000000 -#define STB_PPU_BASE_ADDR 0xC0010000 -#define STB_SC_BASE_ADDRESS 0xC0020000 -#define STB_I2C1_BASE_ADDRESS 0xC0030000 -#define STB_SCC_BASE_ADDRESS 0xC0040000 -#define STB_TIMERS_BASE_ADDRESS 0xC0050000 -#define STB_GPIO0_BASE_ADDRESS 0xC0060000 -#define STB_GPIO1_BASE_ADDRESS 0xC0070000 -#define STB_GPIO2_BASE_ADDRESS 0xC0080000 -#define STB_GPIO3_BASE_ADDRESS 0xC0090000 -#define STB_GPIO4_BASE_ADDRESS 0xC00A0000 -#define STB_I2C2_BASE_ADDRESS 0xC00B0000 -#define STB_SCP_BASE_ADDRESS 0xC00C0000 -#define STB_SSP_BASE_ADDRESS 0xC00D0000 -#define STB_SDRAM_BASE_ADDRESS 0xA0000000 -#endif - -/*----------------------------------------------------------------------------+ -| Other common defines. -+----------------------------------------------------------------------------*/ -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -#endif /* _stb_h_ */ |