diff options
| author | Paul Burton <paul.burton@mips.com> | 2016-09-02 18:10:06 +0300 |
|---|---|---|
| committer | Paul Burton <paul.burton@mips.com> | 2018-06-24 19:27:27 +0300 |
| commit | a07539c00046dfa890e6aac1db4f0de01acb0132 (patch) | |
| tree | e6eed50092c42efae5a5f3e725bafbeb3deb0954 /arch/mips | |
| parent | d1c5872ce1042d10d44e54b6e8e8f5b7c2e76541 (diff) | |
| download | linux-a07539c00046dfa890e6aac1db4f0de01acb0132.tar.xz | |
MIPS: Malta: Cleanup DMA coherence #ifdefs
DMA coherence is not user-selectable in Kconfig, and Malta selects
CONFIG_DMA_MAYBE_COHERENT which in turn selects CONFIG_DMA_NONCOHERENT.
Remove #ifdefs whose conditions can therefore never be true for Malta.
This removes a significant amount of code from bonito_quirks_setup(),
but the code is duplicated in plat_enable_iocoherency() anyway so we
lose nothing but duplication.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/14188/
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/mti-malta/malta-setup.c | 38 |
1 files changed, 0 insertions, 38 deletions
diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c index 7cb7d5a42087..5d4c5e5fbd69 100644 --- a/arch/mips/mti-malta/malta-setup.c +++ b/arch/mips/mti-malta/malta-setup.c @@ -145,12 +145,6 @@ static int __init plat_enable_iocoherency(void) static void __init plat_setup_iocoherency(void) { -#ifdef CONFIG_DMA_NONCOHERENT - /* - * Kernel has been configured with software coherency - * but we might choose to turn it off and use hardware - * coherency instead. - */ if (plat_enable_iocoherency()) { if (coherentio == IO_COHERENCE_DISABLED) pr_info("Hardware DMA cache coherency disabled\n"); @@ -162,10 +156,6 @@ static void __init plat_setup_iocoherency(void) else pr_info("Software DMA cache coherency enabled\n"); } -#else - if (!plat_enable_iocoherency()) - panic("Hardware DMA cache coherency not supported!"); -#endif } static void __init pci_clock_check(void) @@ -227,29 +217,6 @@ static void __init bonito_quirks_setup(void) pr_info("Enabled Bonito debug mode\n"); } else BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE; - -#ifndef CONFIG_DMA_NONCOHERENT - if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { - BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; - pr_info("Enabled Bonito CPU coherency\n"); - - argptr = fw_getcmdline(); - if (strstr(argptr, "iobcuncached")) { - BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; - BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & - ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | - BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); - pr_info("Disabled Bonito IOBC coherency\n"); - } else { - BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; - BONITO_PCIMEMBASECFG |= - (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | - BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); - pr_info("Enabled Bonito IOBC coherency\n"); - } - } else - panic("Hardware DMA cache coherency not supported"); -#endif } void __init *plat_get_fdt(void) @@ -280,11 +247,6 @@ void __init plat_mem_setup(void) */ enable_dma(4); -#ifndef CONFIG_DMA_NONCOHERENT - if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO) - panic("Hardware DMA cache coherency not supported"); -#endif - if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) bonito_quirks_setup(); |