summaryrefslogtreecommitdiff
path: root/arch/mips/mm
diff options
context:
space:
mode:
authorThomas Bogendoerfer <tsbogend@alpha.franken.de>2023-06-15 12:39:33 +0300
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>2023-06-20 15:30:35 +0300
commit13e6b8122d448b07d16a3d9c0d0ab41d00a3f284 (patch)
treee9689493a3d911244c9bde335fc970effa5cc75f /arch/mips/mm
parent5cad8323040bb8d47e130c10ea4dcb7175c7602a (diff)
downloadlinux-13e6b8122d448b07d16a3d9c0d0ab41d00a3f284.tar.xz
MIPS: mm: Remove special handling for OCTEON CPUs
Macro cpu_has_mips_r2_exec_hazard correctly handles OCTEON CPUs, so we don't need the extra switch cases for them. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/mm')
-rw-r--r--arch/mips/mm/tlbex.c24
1 files changed, 4 insertions, 20 deletions
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 80e05ee98d62..8d514a9082c6 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -2123,16 +2123,8 @@ static void build_r4000_tlb_load_handler(void)
uasm_i_tlbr(&p);
- switch (current_cpu_type()) {
- case CPU_CAVIUM_OCTEON:
- case CPU_CAVIUM_OCTEON_PLUS:
- case CPU_CAVIUM_OCTEON2:
- break;
- default:
- if (cpu_has_mips_r2_exec_hazard)
- uasm_i_ehb(&p);
- break;
- }
+ if (cpu_has_mips_r2_exec_hazard)
+ uasm_i_ehb(&p);
/* Examine entrylo 0 or 1 based on ptr. */
if (use_bbit_insns()) {
@@ -2197,16 +2189,8 @@ static void build_r4000_tlb_load_handler(void)
uasm_i_tlbr(&p);
- switch (current_cpu_type()) {
- case CPU_CAVIUM_OCTEON:
- case CPU_CAVIUM_OCTEON_PLUS:
- case CPU_CAVIUM_OCTEON2:
- break;
- default:
- if (cpu_has_mips_r2_exec_hazard)
- uasm_i_ehb(&p);
- break;
- }
+ if (cpu_has_mips_r2_exec_hazard)
+ uasm_i_ehb(&p);
/* Examine entrylo 0 or 1 based on ptr. */
if (use_bbit_insns()) {