diff options
| author | John Crispin <blogic@openwrt.org> | 2012-08-16 12:25:42 +0400 |
|---|---|---|
| committer | John Crispin <blogic@openwrt.org> | 2012-08-23 02:08:18 +0400 |
| commit | f40e1f9d856ec417468c090c4b56826171daa670 (patch) | |
| tree | 473073168643374dfec8caca3199286c85705793 /arch/mips/lantiq/xway | |
| parent | 3a6ac5004c7c8b140319439f8b1f3f6d4cbfe67a (diff) | |
| download | linux-f40e1f9d856ec417468c090c4b56826171daa670.tar.xz | |
MIPS: lantiq: enable pci clk conditional for xrx200 SoC
The xrx200 SoC family has the same PCI clock register layout as the AR9.
Enable the same quirk as for AR9
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4235/
Diffstat (limited to 'arch/mips/lantiq/xway')
| -rw-r--r-- | arch/mips/lantiq/xway/sysctrl.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c index befbb760ab76..67c3a91e54e7 100644 --- a/arch/mips/lantiq/xway/sysctrl.c +++ b/arch/mips/lantiq/xway/sysctrl.c @@ -145,7 +145,8 @@ static int pci_enable(struct clk *clk) { unsigned int val = ltq_cgu_r32(ifccr); /* set bus clock speed */ - if (of_machine_is_compatible("lantiq,ar9")) { + if (of_machine_is_compatible("lantiq,ar9") || + of_machine_is_compatible("lantiq,vr9")) { val &= ~0x1f00000; if (clk->rate == CLOCK_33M) val |= 0xe00000; |