From f40e1f9d856ec417468c090c4b56826171daa670 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Thu, 16 Aug 2012 08:25:42 +0000 Subject: MIPS: lantiq: enable pci clk conditional for xrx200 SoC The xrx200 SoC family has the same PCI clock register layout as the AR9. Enable the same quirk as for AR9 Signed-off-by: John Crispin Patchwork: http://patchwork.linux-mips.org/patch/4235/ --- arch/mips/lantiq/xway/sysctrl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/mips/lantiq/xway') diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c index befbb760ab76..67c3a91e54e7 100644 --- a/arch/mips/lantiq/xway/sysctrl.c +++ b/arch/mips/lantiq/xway/sysctrl.c @@ -145,7 +145,8 @@ static int pci_enable(struct clk *clk) { unsigned int val = ltq_cgu_r32(ifccr); /* set bus clock speed */ - if (of_machine_is_compatible("lantiq,ar9")) { + if (of_machine_is_compatible("lantiq,ar9") || + of_machine_is_compatible("lantiq,vr9")) { val &= ~0x1f00000; if (clk->rate == CLOCK_33M) val |= 0xe00000; -- cgit v1.2.3