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| author | Ingo Molnar <mingo@elte.hu> | 2009-03-13 03:33:21 +0300 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2009-03-13 03:33:21 +0300 |
| commit | 480c93df5b99699390f93a7024c9f60d09da0e96 (patch) | |
| tree | b93b6c8c71c5f2e716dd05b126e01ef4e20ff0af /arch/mips/include | |
| parent | aecfcde920da8d32949f6cbbc1fc051b4ef9e7be (diff) | |
| parent | d820ac4c2fa881079e6b689d2098adce337558ae (diff) | |
| download | linux-480c93df5b99699390f93a7024c9f60d09da0e96.tar.xz | |
Merge branch 'core/locking' into tracing/ftrace
Diffstat (limited to 'arch/mips/include')
| -rw-r--r-- | arch/mips/include/asm/hazards.h | 3 | ||||
| -rw-r--r-- | arch/mips/include/asm/prefetch.h | 2 |
2 files changed, 3 insertions, 2 deletions
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h index 43baed16a109..134e1fc8f4d6 100644 --- a/arch/mips/include/asm/hazards.h +++ b/arch/mips/include/asm/hazards.h @@ -138,7 +138,8 @@ do { \ __instruction_hazard(); \ } while (0) -#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) +#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ + defined(CONFIG_CPU_R5500) /* * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. diff --git a/arch/mips/include/asm/prefetch.h b/arch/mips/include/asm/prefetch.h index 17850834ccb0..a56594f360ee 100644 --- a/arch/mips/include/asm/prefetch.h +++ b/arch/mips/include/asm/prefetch.h @@ -26,7 +26,7 @@ * Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in * current versions due to erratum G105. * - * VR7701 only implements the Load prefetch. + * VR5500 (including VR5701 and VR7701) only implement load prefetch. * * Finally MIPS32 and MIPS64 implement all of the following hints. */ |