diff options
| author | Jonas Gorski <jonas.gorski@gmail.com> | 2012-10-28 16:17:55 +0400 |
|---|---|---|
| committer | John Crispin <blogic@openwrt.org> | 2012-11-09 14:37:18 +0400 |
| commit | ba00e2e5c24f447fb09437a99df697787103f0cd (patch) | |
| tree | 89188f75eb09cca6daea06d327fa3689b1151fda /arch/mips/bcm63xx/clk.c | |
| parent | 799faa626c71fbd92396abea28f7e3586de3c7f5 (diff) | |
| download | linux-ba00e2e5c24f447fb09437a99df697787103f0cd.tar.xz | |
MIPS: BCM63XX: use the new reset helper
Use the new reset helper where appropriate.
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4453
Signed-off-by: John Crispin <blogic@openwrt.org>
Diffstat (limited to 'arch/mips/bcm63xx/clk.c')
| -rw-r--r-- | arch/mips/bcm63xx/clk.c | 19 |
1 files changed, 5 insertions, 14 deletions
diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c index 89a5fb077862..b9e948d59430 100644 --- a/arch/mips/bcm63xx/clk.c +++ b/arch/mips/bcm63xx/clk.c @@ -14,6 +14,7 @@ #include <bcm63xx_cpu.h> #include <bcm63xx_io.h> #include <bcm63xx_regs.h> +#include <bcm63xx_reset.h> #include <bcm63xx_clk.h> static DEFINE_MUTEX(clocks_mutex); @@ -124,15 +125,10 @@ static void enetsw_set(struct clk *clk, int enable) CKCTL_6368_SWPKT_USB_EN | CKCTL_6368_SWPKT_SAR_EN, enable); if (enable) { - u32 val; - /* reset switch core afer clock change */ - val = bcm_perf_readl(PERF_SOFTRESET_6368_REG); - val &= ~SOFTRESET_6368_ENETSW_MASK; - bcm_perf_writel(val, PERF_SOFTRESET_6368_REG); + bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 1); msleep(10); - val |= SOFTRESET_6368_ENETSW_MASK; - bcm_perf_writel(val, PERF_SOFTRESET_6368_REG); + bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 0); msleep(10); } } @@ -222,15 +218,10 @@ static void xtm_set(struct clk *clk, int enable) CKCTL_6368_SWPKT_SAR_EN, enable); if (enable) { - u32 val; - /* reset sar core afer clock change */ - val = bcm_perf_readl(PERF_SOFTRESET_6368_REG); - val &= ~SOFTRESET_6368_SAR_MASK; - bcm_perf_writel(val, PERF_SOFTRESET_6368_REG); + bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 1); mdelay(1); - val |= SOFTRESET_6368_SAR_MASK; - bcm_perf_writel(val, PERF_SOFTRESET_6368_REG); + bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 0); mdelay(1); } } |