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| author | Huacai Chen <chenhuacai@loongson.cn> | 2022-05-31 13:04:12 +0300 |
|---|---|---|
| committer | Huacai Chen <chenhuacai@loongson.cn> | 2022-06-03 15:09:29 +0300 |
| commit | d4b6f1562a3c3284adcef81d6e4f183d7d34b8a9 (patch) | |
| tree | 365dc4b9e63fe8b038078a8fe6e8b8acb32527b1 /arch/loongarch/kernel/traps.c | |
| parent | 46859ac8af52ae599e1b51992ddef3eb43f295fc (diff) | |
| download | linux-d4b6f1562a3c3284adcef81d6e4f183d7d34b8a9.tar.xz | |
LoongArch: Add Non-Uniform Memory Access (NUMA) support
Add Non-Uniform Memory Access (NUMA) support for LoongArch. LoongArch
has 48-bit physical address, but the HyperTransport I/O bus only support
40-bit address, so we need a custom phys_to_dma() and dma_to_phys() to
extract the 4-bit node id (bit 44~47) from Loongson-3's 48-bit physical
address space and embed it into 40-bit. In the 40-bit dma address, node
id offset can be read from the LS7A_DMA_CFG register.
Reviewed-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Diffstat (limited to 'arch/loongarch/kernel/traps.c')
| -rw-r--r-- | arch/loongarch/kernel/traps.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c index 8be071b265b3..e4060f84a221 100644 --- a/arch/loongarch/kernel/traps.c +++ b/arch/loongarch/kernel/traps.c @@ -630,7 +630,7 @@ asmlinkage void noinstr do_vint(struct pt_regs *regs, unsigned long sp) irqentry_exit(regs, state); } -extern void tlb_init(void); +extern void tlb_init(int cpu); extern void cache_error_setup(void); unsigned long eentry; @@ -669,7 +669,7 @@ void per_cpu_trap_init(int cpu) for (i = 0; i < 64; i++) set_handler(i * VECSIZE, handle_reserved, VECSIZE); - tlb_init(); + tlb_init(cpu); cpu_cache_init(); } |