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| author | Huacai Chen <chenhuacai@loongson.cn> | 2022-05-31 13:04:12 +0300 |
|---|---|---|
| committer | Huacai Chen <chenhuacai@loongson.cn> | 2022-06-03 15:09:29 +0300 |
| commit | 46859ac8af52ae599e1b51992ddef3eb43f295fc (patch) | |
| tree | c1e6640316d5d8748bea046b71d2260b81cbe314 /arch/loongarch/kernel/head.S | |
| parent | c6b99bed6b8f3255bd2f65a8e606352e0e638ad0 (diff) | |
| download | linux-46859ac8af52ae599e1b51992ddef3eb43f295fc.tar.xz | |
LoongArch: Add multi-processor (SMP) support
LoongArch-based procesors have 4, 8 or 16 cores per package. This patch
adds multi-processor (SMP) support for LoongArch.
Reviewed-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Diffstat (limited to 'arch/loongarch/kernel/head.S')
| -rw-r--r-- | arch/loongarch/kernel/head.S | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/loongarch/kernel/head.S b/arch/loongarch/kernel/head.S index 57dabb699bb7..e596dfcd924b 100644 --- a/arch/loongarch/kernel/head.S +++ b/arch/loongarch/kernel/head.S @@ -65,4 +65,34 @@ SYM_CODE_START(kernel_entry) # kernel entry point SYM_CODE_END(kernel_entry) +#ifdef CONFIG_SMP + +/* + * SMP slave cpus entry point. Board specific code for bootstrap calls this + * function after setting up the stack and tp registers. + */ +SYM_CODE_START(smpboot_entry) + li.d t0, CSR_DMW0_INIT # UC, PLV0 + csrwr t0, LOONGARCH_CSR_DMWIN0 + li.d t0, CSR_DMW1_INIT # CA, PLV0 + csrwr t0, LOONGARCH_CSR_DMWIN1 + li.w t0, 0xb0 # PLV=0, IE=0, PG=1 + csrwr t0, LOONGARCH_CSR_CRMD + li.w t0, 0x04 # PLV=0, PIE=1, PWE=0 + csrwr t0, LOONGARCH_CSR_PRMD + li.w t0, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0 + csrwr t0, LOONGARCH_CSR_EUEN + + la.abs t0, cpuboot_data + ld.d sp, t0, CPU_BOOT_STACK + ld.d tp, t0, CPU_BOOT_TINFO + + la.abs t0, 0f + jirl zero, t0, 0 +0: + bl start_secondary +SYM_CODE_END(smpboot_entry) + +#endif /* CONFIG_SMP */ + SYM_ENTRY(kernel_entry_end, SYM_L_GLOBAL, SYM_A_NONE) |