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| author | Guo Ren <guoren@linux.alibaba.com> | 2020-12-24 08:59:57 +0300 |
|---|---|---|
| committer | Guo Ren <guoren@linux.alibaba.com> | 2021-01-12 04:52:41 +0300 |
| commit | 3b756ccddb8a75563900cd603c83160b43f3d691 (patch) | |
| tree | af6428140af2760616d577a0b1e515a45b58207c /arch/csky/include/asm | |
| parent | c109f42450ec25283169dd6c0acce8d053493732 (diff) | |
| download | linux-3b756ccddb8a75563900cd603c83160b43f3d691.tar.xz | |
csky: Fix TLB maintenance synchronization problem
TLB invalidate didn't contain a barrier operation in csky cpu and
we need to prevent previous PTW response after TLB invalidation
instruction. Of cause, the ASID changing also needs to take care
of the issue.
CPU0 CPU1
=============== ===============
set_pte
sync_is() -> See the previous set_pte for all harts
tlbi.vas -> Invalidate all harts TLB entry & flush pipeline
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Diffstat (limited to 'arch/csky/include/asm')
| -rw-r--r-- | arch/csky/include/asm/mmu_context.h | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/csky/include/asm/mmu_context.h b/arch/csky/include/asm/mmu_context.h index 3767dbffd02f..594167bbdc63 100644 --- a/arch/csky/include/asm/mmu_context.h +++ b/arch/csky/include/asm/mmu_context.h @@ -30,8 +30,7 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next, if (prev != next) check_and_switch_context(next, cpu); - setup_pgd(next->pgd); - write_mmu_entryhi(next->context.asid.counter); + setup_pgd(next->pgd, next->context.asid.counter); flush_icache_deferred(next); } |