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| author | Icenowy Zheng <icenowy@aosc.io> | 2020-09-23 04:01:21 +0300 |
|---|---|---|
| committer | Maxime Ripard <maxime@cerno.tech> | 2020-09-28 13:09:22 +0300 |
| commit | e174afa66e09e0f836c581c082fbdd73e8875209 (patch) | |
| tree | 1abbf8f05a52b994a832974d04ba5583de4169a4 /arch/arm | |
| parent | 90e048101fa192e6e1ea48192fa22d8c684a0bf1 (diff) | |
| download | linux-e174afa66e09e0f836c581c082fbdd73e8875209.tar.xz | |
ARM: dts: sun8i: V3/V3s/S3/S3L: add pinctrl for 8-bit parallel CSI
The CSI1 controller of V3/V3s/S3/S3L SoCs is used for parallel CSI.
As we're going to add support for Pine64 SCC board, which uses 8-bit
parallel CSI (and the MCLK output), add the pinctrl node of 8-bit
CSI and MCLK to the DTSI file.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20200923010122.148661-1-icenowy@aosc.io
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/sun8i-v3s.dtsi | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 3e079973672d..19fba1a9115b 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -312,6 +312,20 @@ interrupt-controller; #interrupt-cells = <3>; + /omit-if-no-ref/ + csi1_8bit_pins: csi1-8bit-pins { + pins = "PE0", "PE2", "PE3", "PE8", "PE9", + "PE10", "PE11", "PE12", "PE13", "PE14", + "PE15"; + function = "csi"; + }; + + /omit-if-no-ref/ + csi1_mclk_pin: csi1-mclk-pin { + pins = "PE1"; + function = "csi"; + }; + i2c0_pins: i2c0-pins { pins = "PB6", "PB7"; function = "i2c0"; |