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| author | Catalin Marinas <catalin.marinas@arm.com> | 2013-05-01 19:34:22 +0400 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2013-06-07 20:58:29 +0400 |
| commit | 7249b79f6b4cc3c2aa9138dca52e535a4c789107 (patch) | |
| tree | af9de4d98b35a9d5d2e0c9e1925ca5c6b18213d6 /arch/arm64 | |
| parent | b5b6c9e9149d8a7c3f1d7b9d0c046c6184e1dd17 (diff) | |
| download | linux-7249b79f6b4cc3c2aa9138dca52e535a4c789107.tar.xz | |
arm64: Do not flush the D-cache for anonymous pages
The D-cache on AArch64 is VIPT non-aliasing, so there is no need to
flush it for anonymous pages.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Reported-by: Will Deacon <will.deacon@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/mm/flush.c | 8 | ||||
| -rw-r--r-- | arch/arm64/mm/mmu.c | 1 |
2 files changed, 3 insertions, 6 deletions
diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c index b9cd7a4deeca..7c716634a671 100644 --- a/arch/arm64/mm/flush.c +++ b/arch/arm64/mm/flush.c @@ -77,14 +77,12 @@ void __flush_dcache_page(struct page *page) void __sync_icache_dcache(pte_t pte, unsigned long addr) { - unsigned long pfn; - struct page *page; + struct page *page = pte_page(pte); - pfn = pte_pfn(pte); - if (!pfn_valid(pfn)) + /* no flushing needed for anonymous pages */ + if (!page_mapping(page)) return; - page = pfn_to_page(pfn); if (!test_and_set_bit(PG_dcache_clean, &page->flags)) { __flush_dcache_page(page); __flush_icache_all(); diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index eeecc9c8ed68..80a369eab637 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -339,7 +339,6 @@ void __init paging_init(void) bootmem_init(); empty_zero_page = virt_to_page(zero_page); - __flush_dcache_page(empty_zero_page); /* * TTBR0 is only used for the identity mapping at this stage. Make it |