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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-03-12 12:02:35 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-04-02 12:07:03 +0300 |
| commit | 0833ec2fc4b1f01a82a83967a6386a0579a85898 (patch) | |
| tree | 4e6a8d2cbc831ea6f86d8995995deed441d02dd2 /arch/arm64 | |
| parent | 3cdce0b531fbf6ad1d06b52c49b191a5b18d59ea (diff) | |
| download | linux-0833ec2fc4b1f01a82a83967a6386a0579a85898.tar.xz | |
arm64: dts: renesas: r8a779h0: Add SCIF nodes
Add device nodes for the Serial Communication Interfaces with FIFO
(SCIF) on the Renesas R-Car V4M (R8A779H0) SoC, including DMA support.
Based on a patch in the BSP by Nghia Nguyen.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/1285062a78f8ec810d2c93366c2c9dc1f883683f.1709741303.git.geert+renesas@glider.be
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index 4bad906bf2cb..3a40b56c4dcf 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -614,6 +614,74 @@ status = "disabled"; }; + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a779h0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 702>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 702>; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a779h0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 703>; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + status = "disabled"; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a779h0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 704>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 704>; + dmas = <&dmac1 0x57>, <&dmac1 0x56>, + <&dmac2 0x57>, <&dmac2 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a779h0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 705>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, + <&scif_clk2>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 705>; + dmas = <&dmac1 0x59>, <&dmac1 0x58>, + <&dmac2 0x59>, <&dmac2 0x58>; + dma-names = "tx", "rx", "tx", "rx"; + status = "disabled"; + }; + dmac1: dma-controller@e7350000 { compatible = "renesas,dmac-r8a779h0", "renesas,rcar-gen4-dmac"; |