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author | Steven Price <steven.price@arm.com> | 2024-10-17 16:14:31 +0300 |
---|---|---|
committer | Catalin Marinas <catalin.marinas@arm.com> | 2024-10-23 12:19:33 +0300 |
commit | 0e9cb5995b2539a332fe65ada6a28a6be55f6e40 (patch) | |
tree | 7d7a504e493d63b28f99445dc5221bd2f5e0a26d /arch/arm64/mm | |
parent | fbf979a01375704fa87c559763209c658593b6f8 (diff) | |
download | linux-0e9cb5995b2539a332fe65ada6a28a6be55f6e40.tar.xz |
arm64: mm: Avoid TLBI when marking pages as valid
When __change_memory_common() is purely setting the valid bit on a PTE
(e.g. via the set_memory_valid() call) there is no need for a TLBI as
either the entry isn't changing (the valid bit was already set) or the
entry was invalid and so should not have been cached in the TLB.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Steven Price <steven.price@arm.com>
Link: https://lore.kernel.org/r/20241017131434.40935-9-steven.price@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/mm')
-rw-r--r-- | arch/arm64/mm/pageattr.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/arm64/mm/pageattr.c b/arch/arm64/mm/pageattr.c index 0e270a1c51e6..547a9e0b46c2 100644 --- a/arch/arm64/mm/pageattr.c +++ b/arch/arm64/mm/pageattr.c @@ -60,7 +60,13 @@ static int __change_memory_common(unsigned long start, unsigned long size, ret = apply_to_page_range(&init_mm, start, size, change_page_range, &data); - flush_tlb_kernel_range(start, start + size); + /* + * If the memory is being made valid without changing any other bits + * then a TLBI isn't required as a non-valid entry cannot be cached in + * the TLB. + */ + if (pgprot_val(set_mask) != PTE_VALID || pgprot_val(clear_mask)) + flush_tlb_kernel_range(start, start + size); return ret; } |