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| author | Masayoshi Mizuma <m.mizuma@jp.fujitsu.com> | 2019-06-14 16:11:41 +0300 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2019-06-17 13:52:47 +0300 |
| commit | 8f5c9037a55b22e847f636f9a39fa98fe67923d1 (patch) | |
| tree | ec49aafa76c82ea1548fabdea1e4f10176c7313c /arch/arm64/kernel | |
| parent | 1a2a66db4967d66402501c43bdfe9d68be54f648 (diff) | |
| download | linux-8f5c9037a55b22e847f636f9a39fa98fe67923d1.tar.xz | |
arm64/mm: Correct the cache line size warning with non coherent device
If the cache line size is greater than ARCH_DMA_MINALIGN (128),
the warning shows and it's tainted as TAINT_CPU_OUT_OF_SPEC.
However, it's not good because as discussed in the thread [1], the cpu
cache line size will be problem only on non-coherent devices.
Since the coherent flag is already introduced to struct device,
show the warning only if the device is non-coherent device and
ARCH_DMA_MINALIGN is smaller than the cpu cache size.
[1] https://lore.kernel.org/linux-arm-kernel/20180514145703.celnlobzn3uh5tc2@localhost/
Signed-off-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
Reviewed-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Tested-by: Zhang Lei <zhang.lei@jp.fujitsu.com>
[catalin.marinas@arm.com: removed 'if' block for WARN_TAINT]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/kernel')
| -rw-r--r-- | arch/arm64/kernel/cacheinfo.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c index 0c0cd4d26b87..969fcc3be556 100644 --- a/arch/arm64/kernel/cacheinfo.c +++ b/arch/arm64/kernel/cacheinfo.c @@ -30,12 +30,10 @@ int cache_line_size(void) { - u32 cwg = cache_type_cwg(); - if (coherency_max_size != 0) return coherency_max_size; - return cwg ? 4 << cwg : ARCH_DMA_MINALIGN; + return cache_line_size_of_cpu(); } EXPORT_SYMBOL_GPL(cache_line_size); |