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| author | Rohit Agarwal <rohiagar@chromium.org> | 2024-08-30 11:45:44 +0300 |
|---|---|---|
| committer | Matthias Brugger <matthias.bgg@gmail.com> | 2024-09-09 17:41:36 +0300 |
| commit | 14fde547d2aa116f7f74d3b31ea35a94e147a8a8 (patch) | |
| tree | 581567c2b6024bb3c4ab6917359e0fe84b27a0b6 /arch/arm64/boot | |
| parent | 7a3852a9ba2e40738fa4ddadb4e94ae68f3826a4 (diff) | |
| download | linux-14fde547d2aa116f7f74d3b31ea35a94e147a8a8.tar.xz | |
arm64: dts: mediatek: mt8186: Add svs node
Add clock/irq/efuse setting in svs nodes for mt8186 SoC.
Signed-off-by: Rohit Agarwal <rohiagar@chromium.org>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20240830084544.2898512-4-rohiagar@chromium.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'arch/arm64/boot')
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8186.dtsi | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index 380071822334..148c332018b0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -1374,6 +1374,18 @@ #thermal-sensor-cells = <1>; }; + svs: svs@1100bc00 { + compatible = "mediatek,mt8186-svs"; + reg = <0 0x1100bc00 0 0x400>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; + clock-names = "main"; + nvmem-cells = <&svs_calibration>, <&lvts_efuse_data1>; + nvmem-cell-names = "svs-calibration-data", "t-calibration-data"; + resets = <&infracfg_ao MT8186_INFRA_PTP_CTRL_RST>; + reset-names = "svs_rst"; + }; + pwm0: pwm@1100e000 { compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm"; reg = <0 0x1100e000 0 0x1000>; @@ -1697,6 +1709,10 @@ reg = <0x2f8 0x14>; }; + svs_calibration: calib@550 { + reg = <0x550 0x50>; + }; + gpu_speedbin: gpu-speedbin@59c { reg = <0x59c 0x4>; bits = <0 3>; |