diff options
author | Michal Simek <michal.simek@amd.com> | 2023-05-02 16:35:37 +0300 |
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committer | Michal Simek <michal.simek@amd.com> | 2023-05-16 15:50:14 +0300 |
commit | e05d2f969cb558da5c74c1e5c6aaf506806f4563 (patch) | |
tree | 6c05ac12849cc06be5876ad0ef4b338e4f63dfd9 /arch/arm64/boot/dts/xilinx | |
parent | 028d125a30ff5646b3ad22445080d8f2946d67d7 (diff) | |
download | linux-e05d2f969cb558da5c74c1e5c6aaf506806f4563.tar.xz |
arm64: zynqmp: Add dmas, dp, rtc, watchdogs and opp nodes for SOM
There are couple of IPs which are enabled in origin HW design which are
missing in SOM dt. Add them to match default setup.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/5d3777fdf91d114effe1921255a7ad71ef30d277.1683034376.git.michal.simek@amd.com
Diffstat (limited to 'arch/arm64/boot/dts/xilinx')
-rw-r--r-- | arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 95 |
1 files changed, 95 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index 34412304d09f..54cf2e817537 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -288,6 +288,101 @@ "", "", "", ""; /* 170 - 173 */ }; +&zynqmp_dpsub { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&lpd_dma_chan1 { + status = "okay"; +}; + +&lpd_dma_chan2 { + status = "okay"; +}; + +&lpd_dma_chan3 { + status = "okay"; +}; + +&lpd_dma_chan4 { + status = "okay"; +}; + +&lpd_dma_chan5 { + status = "okay"; +}; + +&lpd_dma_chan6 { + status = "okay"; +}; + +&lpd_dma_chan7 { + status = "okay"; +}; + +&lpd_dma_chan8 { + status = "okay"; +}; + +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +}; + &gpu { status = "okay"; }; + +&lpd_watchdog { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; + +&cpu_opp_table { + opp00 { + opp-hz = /bits/ 64 <1333333333>; + }; + opp01 { + opp-hz = /bits/ 64 <666666666>; + }; + opp02 { + opp-hz = /bits/ 64 <444444444>; + }; + opp03 { + opp-hz = /bits/ 64 <333333333>; + }; +}; |