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| author | George Cherian <george.cherian@cavium.com> | 2018-03-23 13:30:31 +0300 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2018-03-30 13:15:58 +0300 |
| commit | 3d41386d556db9f720e00de3e11e45f39cb5071c (patch) | |
| tree | 3b04b6dfe0445d3e13f2ba7da722011a6fec894a /arch/arm64/boot/dts/rockchip/rk3399.dtsi | |
| parent | a8b6966034ba88190eca397e2693b5bc16790517 (diff) | |
| download | linux-3d41386d556db9f720e00de3e11e45f39cb5071c.tar.xz | |
cpufreq: CPPC: Use transition_delay_us depending transition_latency
With commit e948bc8fbee0 (cpufreq: Cap the default transition delay
value to 10 ms) the cpufreq was not honouring the delay passed via
ACPI (PCCT). Due to which on ARM based platforms using CPPC the
cpufreq governor tries to change the frequency of CPUs faster than
expected.
This leads to continuous error messages like the following.
" ACPI CPPC: PCC check channel failed. Status=0 "
Earlier (without above commit) the default transition delay was
taken form the value passed from PCCT. Use the same value provided
by PCCT to set the transition_delay_us.
Fixes: e948bc8fbee0 (cpufreq: Cap the default transition delay value to 10 ms)
Signed-off-by: George Cherian <george.cherian@cavium.com>
Cc: 4.14+ <stable@vger.kernel.org> # 4.14+
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3399.dtsi')
0 files changed, 0 insertions, 0 deletions