diff options
| author | Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2023-10-10 16:27:01 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-10-12 20:58:10 +0300 |
| commit | 1d071ea156aaa5942564282d69866596b6de95c9 (patch) | |
| tree | 97cf8ccda21a82c02576d88b6f07d59c9f53d8dc /arch/arm64/boot/dts/renesas/r9a08g045.dtsi | |
| parent | 6a35583085a70bbf37e8f905e098a1dae5711165 (diff) | |
| download | linux-1d071ea156aaa5942564282d69866596b6de95c9.tar.xz | |
arm64: dts: renesas: r9a08g045: Add missing cache-level for L3 cache
Fix the following DTBS check warnings:
arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dtb: cache-controller-0: 'cache-level' is a required property
from schema $id: http://devicetree.org/schemas/cache.yaml#
arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dtb: cache-controller-0: 'cache-level' is a required property
from schema $id: http://devicetree.org/schemas/cache.yaml#
arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dtb: cache-controller-0: Unevaluated properties are not allowed ('cache-size', 'cache-unified' were unexpected)
from schema $id: http://devicetree.org/schemas/cache.yaml#
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231010132701.1658737-7-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r9a08g045.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 534b728a8e14..6c7b29b69d0e 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -29,6 +29,7 @@ L3_CA55: cache-controller-0 { compatible = "cache"; + cache-level = <3>; cache-unified; cache-size = <0x40000>; }; |