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authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>2022-02-27 23:37:38 +0300
committerGeert Uytterhoeven <geert+renesas@glider.be>2022-04-04 12:05:45 +0300
commit8d3da65c4c40d77977799f58fa6465bdc723536f (patch)
treebf0689b6ff02cb8370802ff177b00571e1b0a44b /arch/arm64/boot/dts/renesas/r9a07g054.dtsi
parente46a72e0398e570fbab5905ea6be67dc76d678f4 (diff)
downloadlinux-8d3da65c4c40d77977799f58fa6465bdc723536f.tar.xz
arm64: dts: renesas: r9a07g054: Fillup the sbc stub node
Fillup the sbc stub node in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220227203744.18355-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r9a07g054.dtsi')
-rw-r--r--arch/arm64/boot/dts/renesas/r9a07g054.dtsi10
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index fafb986fe3bc..1207a99bf3fe 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -398,12 +398,20 @@
};
sbc: spi@10060000 {
+ compatible = "renesas,r9a07g054-rpc-if",
+ "renesas,rzg2l-rpc-if";
reg = <0 0x10060000 0 0x10000>,
<0 0x20000000 0 0x10000000>,
<0 0x10070000 0 0x10000>;
+ reg-names = "regs", "dirmap", "wbuf";
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G054_SPI_CLK2>,
+ <&cpg CPG_MOD R9A07G054_SPI_CLK>;
+ resets = <&cpg R9A07G054_SPI_RST>;
+ power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
- /* place holder */
+ status = "disabled";
};
cpg: clock-controller@11010000 {