Merge tag 'dt-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC DT updates from Arnd Bergmann:
 "This is a rather large update for the ARM devicetree files, after a
  few quieter releases, with 775 total commits and 47 branches pulled
  into this one.

  There are 5 new SoC types plus some minor variations, and a total of
  60 new machines, so I'm limiting the summary to the main noteworthy
  items:

   - Apple M1 gain support for PCI and pinctrl, getting a bit closer to
     a usable system out of the box.

   - Qualcomm gains support for Snapdragon 690 (aka SM6350) as well as
     SM7225, 11 new smartphones, and three additional Chromebooks, and
     improvements all over the place.

   - Samsung gains support for ExynosAutov9, an automotive version of
     their smartphone SoC, but otherwise no major changes.

   - Microchip adds the SAMA5D29 SoC in the SAMA5 family, and a number
     of improvements for the recently added SAMA7 family. The LAN966 SoC
     that was added in the platform code does not have dts files yet.
     Two board files are added for the older at91sam9g20 SoC

   - Aspeed supports two additional server boards using their AST2600 as
     BMC, and improves support for qemu models

   - Rockchip RK3566/RK3688 gets added, along with six new development
     boards using RK3328/RK3399/RK3566, and one Chromebook tablet.

   - Two NAS boxes are added using the ARMv4 based Gemini platform

   - One new board is added to the Intel Arria SoC FPGA family

   - Marvell adds one network switch based on Armada 381 and the new
     MOCHAbin 7040 development board

   - NXP adds support for the S32G2 automotive SoC, two imx6 based ebook
     readers, and three additional development boards, which is notably
     less than their usual additions, but they also gain improvements to
     their many existing boards

   - STmicroelectronics adds their stm32mp13 SoC family along with a
     reference board

   - Renesas adds new versions of their R-Car Gen3 SoCs and many updates
     for their older generations

   - Broadcom adds support for a number of Cisco Meraki wireless
     controllers, along with two new boards and other updates for
     BCM53xx/BCM47xx networking SoCs and the Raspberry Pi boards

   - Mediatek improves support for the MT81xx SoCs used in Chromebooks
     as well as the MT76xx networking SoCs

   - NVIDIA adds a number of cleanups and additional support for more
     hardware on the already supported machines

   - TI K3 adds support for three new boards along with cleanups

   - Toshiba adds one board for the Visconti family

   - Xilinx adds five new ZynqMP based machines

   - Amlogic support is added for the Radxa Zero and two Jethub home
     automation controllers, along with changes to other machines

   - Rob Herring continues his work on fixing dtc warnings all over the
     tree.

   - Minor updates for TI OMAP, Mstar, Allwinner/sunxi, Hisilicon,
     Ux500, Unisoc"

* tag 'dt-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (720 commits)
  arm64: dts: apple: j274: Expose PCI node for the Ethernet MAC address
  arm64: dts: apple: t8103: Add root port interrupt routing
  arm64: dts: apple: t8103: Add PCIe DARTs
  arm64: apple: Add PCIe node
  arm64: apple: Add pinctrl nodes
  ARM: dts: arm: Update ICST clock nodes 'reg' and node names
  ARM: dts: arm: Update register-bit-led nodes 'reg' and node names
  arm64: dts: exynos: add chipid node for exynosautov9 SoC
  ARM: dts: qcom: fix typo in IPQ8064 thermal-sensor node
  Revert "arm64: dts: qcom: msm8916-asus-z00l: Add sensors"
  arm64: dts: qcom: ipq6018: Remove unused 'iface_clk' property from dma-controller node
  arm64: dts: qcom: ipq6018: Remove unused 'qcom,config-pipe-trust-reg' property
  arm64: dts: qcom: sm8350: Add CPU topology and idle-states
  arm64: dts: qcom: Drop unneeded extra device-specific includes
  arm64: dts: qcom: msm8916: Drop standalone smem node
  arm64: dts: qcom: Fix node name of rpm-msg-ram device nodes
  arm64: dts: qcom: msm8916-asus-z00l: Add sensors
  arm64: dts: qcom: msm8916-asus-z00l: Add SDCard
  arm64: dts: qcom: msm8916-asus-z00l: Add touchscreen
  arm64: dts: qcom: sdm845-oneplus: remove devinfo-size from ramoops node
  ...

1 files changed, 76 insertions, 16 deletions

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index db333001df4d..6c6a0f853669 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -91,7 +91,6 @@
 		ssphy_1: phy@58000 {
 			compatible = "qcom,ipq8074-qmp-usb3-phy";
 			reg = <0x00058000 0x1c4>;
-			#clock-cells = <1>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges;
@@ -106,12 +105,13 @@
 			reset-names = "phy","common";
 			status = "disabled";
 
-			usb1_ssphy: lane@58200 {
+			usb1_ssphy: phy@58200 {
 				reg = <0x00058200 0x130>,       /* Tx */
 				      <0x00058400 0x200>,     /* Rx */
 				      <0x00058800 0x1f8>,     /* PCS  */
 				      <0x00058600 0x044>;     /* PCS misc*/
 				#phy-cells = <0>;
+				#clock-cells = <1>;
 				clocks = <&gcc GCC_USB1_PIPE_CLK>;
 				clock-names = "pipe0";
 				clock-output-names = "gcc_usb1_pipe_clk_src";
@@ -134,7 +134,6 @@
 		ssphy_0: phy@78000 {
 			compatible = "qcom,ipq8074-qmp-usb3-phy";
 			reg = <0x00078000 0x1c4>;
-			#clock-cells = <1>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges;
@@ -149,12 +148,13 @@
 			reset-names = "phy","common";
 			status = "disabled";
 
-			usb0_ssphy: lane@78200 {
+			usb0_ssphy: phy@78200 {
 				reg = <0x00078200 0x130>,       /* Tx */
 				      <0x00078400 0x200>,     /* Rx */
 				      <0x00078800 0x1f8>,     /* PCS  */
 				      <0x00078600 0x044>;     /* PCS misc*/
 				#phy-cells = <0>;
+				#clock-cells = <1>;
 				clocks = <&gcc GCC_USB0_PIPE_CLK>;
 				clock-names = "pipe0";
 				clock-output-names = "gcc_usb0_pipe_clk_src";
@@ -174,34 +174,60 @@
 			status = "disabled";
 		};
 
-		pcie_phy0: phy@86000 {
+		pcie_qmp0: phy@86000 {
 			compatible = "qcom,ipq8074-qmp-pcie-phy";
 			reg = <0x00086000 0x1000>;
-			#phy-cells = <0>;
-			clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
-			clock-names = "pipe_clk";
-			clock-output-names = "pcie20_phy0_pipe_clk";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
 
+			clocks = <&gcc GCC_PCIE0_AUX_CLK>,
+				<&gcc GCC_PCIE0_AHB_CLK>;
+			clock-names = "aux", "cfg_ahb";
 			resets = <&gcc GCC_PCIE0_PHY_BCR>,
 				<&gcc GCC_PCIE0PHY_PHY_BCR>;
 			reset-names = "phy",
 				      "common";
 			status = "disabled";
+
+			pcie_phy0: phy@86200 {
+				reg = <0x86200 0x16c>,
+				      <0x86400 0x200>,
+				      <0x86800 0x4f4>;
+				#phy-cells = <0>;
+				#clock-cells = <0>;
+				clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
+				clock-names = "pipe0";
+				clock-output-names = "pcie_0_pipe_clk";
+			};
 		};
 
-		pcie_phy1: phy@8e000 {
+		pcie_qmp1: phy@8e000 {
 			compatible = "qcom,ipq8074-qmp-pcie-phy";
 			reg = <0x0008e000 0x1000>;
-			#phy-cells = <0>;
-			clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
-			clock-names = "pipe_clk";
-			clock-output-names = "pcie20_phy1_pipe_clk";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
 
+			clocks = <&gcc GCC_PCIE1_AUX_CLK>,
+				<&gcc GCC_PCIE1_AHB_CLK>;
+			clock-names = "aux", "cfg_ahb";
 			resets = <&gcc GCC_PCIE1_PHY_BCR>,
 				<&gcc GCC_PCIE1PHY_PHY_BCR>;
 			reset-names = "phy",
 				      "common";
 			status = "disabled";
+
+			pcie_phy1: phy@8e200 {
+				reg = <0x8e200 0x16c>,
+				      <0x8e400 0x200>,
+				      <0x8e800 0x4f4>;
+				#phy-cells = <0>;
+				#clock-cells = <0>;
+				clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
+				clock-names = "pipe0";
+				clock-output-names = "pcie_1_pipe_clk";
+			};
 		};
 
 		prng: rng@e3000 {
@@ -212,7 +238,7 @@
 			status = "disabled";
 		};
 
-		cryptobam: dma@704000 {
+		cryptobam: dma-controller@704000 {
 			compatible = "qcom,bam-v1.7.0";
 			reg = <0x00704000 0x20000>;
 			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
@@ -220,7 +246,7 @@
 			clock-names = "bam_clk";
 			#dma-cells = <1>;
 			qcom,ee = <1>;
-			qcom,controlled-remotely = <1>;
+			qcom,controlled-remotely;
 			status = "disabled";
 		};
 
@@ -293,6 +319,25 @@
 			#reset-cells = <0x1>;
 		};
 
+		spmi_bus: spmi@200f000 {
+			compatible = "qcom,spmi-pmic-arb";
+			reg = <0x0200f000 0x001000>,
+			      <0x02400000 0x800000>,
+			      <0x02c00000 0x800000>,
+			      <0x03800000 0x200000>,
+			      <0x0200a000 0x000700>;
+			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "periph_irq";
+			qcom,ee = <0>;
+			qcom,channel = <0>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			interrupt-controller;
+			#interrupt-cells = <4>;
+			cell-index = <0>;
+		};
+
 		sdhc_1: sdhci@7824900 {
 			compatible = "qcom,sdhci-msm-v4";
 			reg = <0x7824900 0x500>, <0x7824000 0x800>;
@@ -411,6 +456,21 @@
 			status = "disabled";
 		};
 
+		blsp1_i2c5: i2c@78b9000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x78b9000 0x600>;
+			interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+				 <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
+			clock-names = "iface", "core";
+			clock-frequency = <400000>;
+			dmas = <&blsp_dma 21>, <&blsp_dma 20>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
 		blsp1_i2c6: i2c@78ba000 {
 			compatible = "qcom,i2c-qup-v2.2.1";
 			#address-cells = <1>;