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author | Konstantin Porotchkin <kostap@marvell.com> | 2021-07-08 15:46:09 +0300 |
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committer | Gregory CLEMENT <gregory.clement@bootlin.com> | 2021-07-23 15:33:11 +0300 |
commit | 4c43a41e5b8ccbeee79330ae7989c301589d38c2 (patch) | |
tree | 24c63ac4bd5126d4f764f65ec908d281008b9344 /arch/arm64/boot/dts/marvell/cn9130-db-B.dts | |
parent | e73f0f0ee7541171d89f2e2491130c7771ba58d3 (diff) | |
download | linux-4c43a41e5b8ccbeee79330ae7989c301589d38c2.tar.xz |
arm64: dts: cn913x: add device trees for topology B boards
The CN913x DB with topology B is similar to a regular setup (A)
boards, but uses NAND flash as a boot device, while topology A
boards are booting from SPI flash.
Since NAND and SPI on CN913x DB boards share some wires, they
cannot be activated simultaneously.
The DTS files for setup "B" are based on setup "A", in which the
CP0 NAND controller enabled and CP0 SPI1 disabled.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to 'arch/arm64/boot/dts/marvell/cn9130-db-B.dts')
-rw-r--r-- | arch/arm64/boot/dts/marvell/cn9130-db-B.dts | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db-B.dts b/arch/arm64/boot/dts/marvell/cn9130-db-B.dts new file mode 100644 index 000000000000..57e41cacd483 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/cn9130-db-B.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Marvell International Ltd. + * + * Device tree for the CN9130-DB board (setup "B"). + */ + +#include "cn9130-db.dtsi" + +/ { + model = "Marvell Armada CN9130-DB setup B"; +}; + +/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash. + * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated + * simultaneously. When NAND controller is enabled, SPI1 should be disabled. + */ + +&cp0_nand_controller { + status = "okay"; +}; + |