arm64: dts: hisilicon: Unify pinctrl-single pin group nodes

We want to unify the pinctrl-single pin group nodes to use naming "pins".
Otherwise non-standad pin group names will add make dtbs checks errors
when the pinctrl-single yaml binding gets merged.

Let's also correct the pinctrl controller #size-cells to 0 while at it.

Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

1 files changed, 59 insertions, 59 deletions

diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi
index 77bd8c3a8314..8f7bf80e6ece 100644
--- a/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi
@@ -21,14 +21,14 @@
 			/* pin base, nr pins & gpio function */
 			pinctrl-single,gpio-range = <&range 0 82 0>;
 
-			uart0_pmx_func: uart0_pmx_func {
+			uart0_pmx_func: uart0-pins {
 				pinctrl-single,pins = <
 					0x054 MUX_M2 /* UART0_RXD */
 					0x058 MUX_M2 /* UART0_TXD */
 				>;
 			};
 
-			uart2_pmx_func: uart2_pmx_func {
+			uart2_pmx_func: uart2-pins {
 				pinctrl-single,pins = <
 					0x700 MUX_M2 /* UART2_CTS_N */
 					0x704 MUX_M2 /* UART2_RTS_N */
@@ -37,7 +37,7 @@
 				>;
 			};
 
-			uart3_pmx_func: uart3_pmx_func {
+			uart3_pmx_func: uart3-pins {
 				pinctrl-single,pins = <
 					0x064 MUX_M1 /* UART3_CTS_N */
 					0x068 MUX_M1 /* UART3_RTS_N */
@@ -46,7 +46,7 @@
 				>;
 			};
 
-			uart4_pmx_func: uart4_pmx_func {
+			uart4_pmx_func: uart4-pins {
 				pinctrl-single,pins = <
 					0x074 MUX_M1 /* UART4_CTS_N */
 					0x078 MUX_M1 /* UART4_RTS_N */
@@ -55,52 +55,52 @@
 				>;
 			};
 
-			uart6_pmx_func: uart6_pmx_func {
+			uart6_pmx_func: uart6-pins {
 				pinctrl-single,pins = <
 					0x05c MUX_M1 /* UART6_RXD */
 					0x060 MUX_M1 /* UART6_TXD */
 				>;
 			};
 
-			i2c3_pmx_func: i2c3_pmx_func {
+			i2c3_pmx_func: i2c3-pins {
 				pinctrl-single,pins = <
 					0x010 MUX_M1 /* I2C3_SCL */
 					0x014 MUX_M1 /* I2C3_SDA */
 				>;
 			};
 
-			i2c4_pmx_func: i2c4_pmx_func {
+			i2c4_pmx_func: i2c4-pins {
 				pinctrl-single,pins = <
 					0x03c MUX_M1 /* I2C4_SCL */
 					0x040 MUX_M1 /* I2C4_SDA */
 				>;
 			};
 
-			cam0_rst_pmx_func: cam0_rst_pmx_func {
+			cam0_rst_pmx_func: cam0-rst-pins {
 				pinctrl-single,pins = <
 					0x714 MUX_M0 /* CAM0_RST */
 				>;
 			};
 
-			cam1_rst_pmx_func: cam1_rst_pmx_func {
+			cam1_rst_pmx_func: cam1-rst-pins {
 				pinctrl-single,pins = <
 					0x048 MUX_M0 /* CAM1_RST */
 				>;
 			};
 
-			cam0_pwd_n_pmx_func: cam0_pwd_n_pmx_func {
+			cam0_pwd_n_pmx_func: cam0-pwd-n-pins {
 				pinctrl-single,pins = <
 					0x098 MUX_M0 /* CAM0_PWD_N */
 				>;
 			};
 
-			cam1_pwd_n_pmx_func: cam1_pwd_n_pmx_func {
+			cam1_pwd_n_pmx_func: cam1-pwd-n-pins {
 				pinctrl-single,pins = <
 					0x044 MUX_M0 /* CAM1_PWD_N */
 				>;
 			};
 
-			isp0_pmx_func: isp0_pmx_func {
+			isp0_pmx_func: isp0-pins {
 				pinctrl-single,pins = <
 					0x018 MUX_M1 /* ISP_CLK0 */
 					0x024 MUX_M1 /* ISP_SCL0 */
@@ -108,7 +108,7 @@
 				>;
 			};
 
-			isp1_pmx_func: isp1_pmx_func {
+			isp1_pmx_func: isp1-pins {
 				pinctrl-single,pins = <
 					0x01c MUX_M1 /* ISP_CLK1 */
 					0x02c MUX_M1 /* ISP_SCL1 */
@@ -127,19 +127,19 @@
 			/* pin base, nr pins & gpio function */
 			pinctrl-single,gpio-range = <&range 0 46 0>;
 
-			pwr_key_pmx_func: pwr_key_pmx_func {
+			pwr_key_pmx_func: pwr-key-pins {
 				pinctrl-single,pins = <
 					0x064 MUX_M0 /* GPIO_203 */
 				>;
 			};
 
-			pd_pmx_func: pd_pmx_func{
+			pd_pmx_func: pd-pins {
 				pinctrl-single,pins = <
 					0x080 MUX_M0 /* GPIO_221 */
 				>;
 			};
 
-			i2s2_pmx_func: i2s2_pmx_func {
+			i2s2_pmx_func: i2s2-pins {
 			    pinctrl-single,pins = <
 					0x050 MUX_M1 /* I2S2_DI */
 					0x054 MUX_M1 /* I2S2_DO */
@@ -148,7 +148,7 @@
 			    >;
 			};
 
-			spi0_pmx_func: spi0_pmx_func {
+			spi0_pmx_func: spi0-pins {
 				pinctrl-single,pins = <
 					0x094 MUX_M1 /* SPI0_CLK */
 					0x098 MUX_M1 /* SPI0_DI */
@@ -157,7 +157,7 @@
 				>;
 			};
 
-			spi2_pmx_func: spi2_pmx_func {
+			spi2_pmx_func: spi2-pins {
 				pinctrl-single,pins = <
 					0x710 MUX_M1 /* SPI2_CLK */
 					0x714 MUX_M1 /* SPI2_DI */
@@ -166,7 +166,7 @@
 				>;
 			};
 
-			spi3_pmx_func: spi3_pmx_func {
+			spi3_pmx_func: spi3-pins {
 				pinctrl-single,pins = <
 					0x72c MUX_M1 /* SPI3_CLK */
 					0x730 MUX_M1 /* SPI3_DI */
@@ -175,37 +175,37 @@
 				>;
 			};
 
-			i2c0_pmx_func: i2c0_pmx_func {
+			i2c0_pmx_func: i2c0-pins {
 				pinctrl-single,pins = <
 					0x020 MUX_M1 /* I2C0_SCL */
 					0x024 MUX_M1 /* I2C0_SDA */
 				>;
 			};
 
-			i2c1_pmx_func: i2c1_pmx_func {
+			i2c1_pmx_func: i2c1-pins {
 				pinctrl-single,pins = <
 					0x028 MUX_M1 /* I2C1_SCL */
 					0x02c MUX_M1 /* I2C1_SDA */
 				>;
 			};
-			i2c2_pmx_func: i2c2_pmx_func {
+			i2c2_pmx_func: i2c2-pins {
 				pinctrl-single,pins = <
 					0x030 MUX_M1 /* I2C2_SCL */
 					0x034 MUX_M1 /* I2C2_SDA */
 				>;
 			};
 
-			pcie_clkreq_pmx_func: pcie_clkreq_pmx_func {
+			pcie_clkreq_pmx_func: pcie-clkreq-pins {
 				pinctrl-single,pins = <
 					0x084 MUX_M1 /* PCIE0_CLKREQ_N */
 				>;
 			};
 
-			gpio185_pmx_func: gpio185_pmx_func {
+			gpio185_pmx_func: gpio185-pins {
 				pinctrl-single,pins = <0x01C    0x1>;
 			};
 
-			gpio185_pmx_idle: gpio185_pmx_idle {
+			gpio185_pmx_idle: gpio185-idle-pins {
 				pinctrl-single,pins = <0x01C    0x0>;
 			};
 		};
@@ -216,7 +216,7 @@
 			#pinctrl-cells = <1>;
 			pinctrl-single,register-width = <0x20>;
 
-			uart0_cfg_func: uart0_cfg_func {
+			uart0_cfg_func: uart0-cfg-pins {
 				pinctrl-single,pins = <
 					0x058 0x0 /* UART0_RXD */
 					0x05c 0x0 /* UART0_TXD */
@@ -238,7 +238,7 @@
 				>;
 			};
 
-			uart2_cfg_func: uart2_cfg_func {
+			uart2_cfg_func: uart2-cfg-pins {
 				pinctrl-single,pins = <
 					0x700 0x0 /* UART2_CTS_N */
 					0x704 0x0 /* UART2_RTS_N */
@@ -262,7 +262,7 @@
 				>;
 			};
 
-			uart3_cfg_func: uart3_cfg_func {
+			uart3_cfg_func: uart3-cfg-pins {
 				pinctrl-single,pins = <
 					0x068 0x0 /* UART3_CTS_N */
 					0x06c 0x0 /* UART3_RTS_N */
@@ -286,7 +286,7 @@
 				>;
 			};
 
-			uart4_cfg_func: uart4_cfg_func {
+			uart4_cfg_func: uart4-cfg-pins {
 				pinctrl-single,pins = <
 					0x078 0x0 /* UART4_CTS_N */
 					0x07c 0x0 /* UART4_RTS_N */
@@ -310,7 +310,7 @@
 				>;
 			};
 
-			uart6_cfg_func: uart6_cfg_func {
+			uart6_cfg_func: uart6-cfg-pins {
 				pinctrl-single,pins = <
 					0x060 0x0 /* UART6_RXD */
 					0x064 0x0 /* UART6_TXD */
@@ -332,7 +332,7 @@
 				>;
 			};
 
-			i2c3_cfg_func: i2c3_cfg_func {
+			i2c3_cfg_func: i2c3-cfg-pins {
 				pinctrl-single,pins = <
 					0x014 0x0 /* I2C3_SCL */
 					0x018 0x0 /* I2C3_SDA */
@@ -354,7 +354,7 @@
 				>;
 			};
 
-			i2c4_cfg_func: i2c4_cfg_func {
+			i2c4_cfg_func: i2c4-cfg-pins {
 				pinctrl-single,pins = <
 					0x040 0x0 /* I2C4_SCL */
 					0x044 0x0 /* I2C4_SDA */
@@ -376,7 +376,7 @@
 				>;
 			};
 
-			cam0_rst_cfg_func: cam0_rst_cfg_func {
+			cam0_rst_cfg_func: cam0-rst-cfg-pins {
 				pinctrl-single,pins = <
 					0x714 0x0 /* CAM0_RST */
 				>;
@@ -397,7 +397,7 @@
 				>;
 			};
 
-			cam1_rst_cfg_func: cam1_rst_cfg_func {
+			cam1_rst_cfg_func: cam1-rst-cfg-pins {
 				pinctrl-single,pins = <
 					0x04C 0x0 /* CAM1_RST */
 				>;
@@ -418,7 +418,7 @@
 				>;
 			};
 
-			cam0_pwd_n_cfg_func: cam0_pwd_n_cfg_func {
+			cam0_pwd_n_cfg_func: cam0-pwd-n-cfg-pins {
 				pinctrl-single,pins = <
 					0x09C 0x0 /* CAM0_PWD_N */
 				>;
@@ -439,7 +439,7 @@
 				>;
 			};
 
-			cam1_pwd_n_cfg_func: cam1_pwd_n_cfg_func {
+			cam1_pwd_n_cfg_func: cam1-pwd-n-cfg-pins {
 				pinctrl-single,pins = <
 					0x048 0x0 /* CAM1_PWD_N */
 				>;
@@ -460,7 +460,7 @@
 				>;
 			};
 
-			isp0_cfg_func: isp0_cfg_func {
+			isp0_cfg_func: isp0-cfg-pins {
 				pinctrl-single,pins = <
 					0x01C 0x0 /* ISP_CLK0 */
 					0x028 0x0 /* ISP_SCL0 */
@@ -483,7 +483,7 @@
 				>;
 			};
 
-			isp1_cfg_func: isp1_cfg_func {
+			isp1_cfg_func: isp1-cfg-pins {
 				pinctrl-single,pins = <
 					0x020 0x0 /* ISP_CLK1 */
 					0x030 0x0 /* ISP_SCL1 */
@@ -517,7 +517,7 @@
 			/* pin base, nr pins & gpio function */
 			pinctrl-single,gpio-range = <&range 0 10 0>;
 
-			sdio_pmx_func: sdio_pmx_func {
+			sdio_pmx_func: sdio-pins {
 				pinctrl-single,pins = <
 					0x000 MUX_M1 /* SDIO_CLK */
 					0x004 MUX_M1 /* SDIO_CMD */
@@ -535,7 +535,7 @@
 			#pinctrl-cells = <1>;
 			pinctrl-single,register-width = <0x20>;
 
-			sdio_clk_cfg_func: sdio_clk_cfg_func {
+			sdio_clk_cfg_func: sdio-clk-cfg-pins {
 				pinctrl-single,pins = <
 					0x000 0x0 /* SDIO_CLK */
 				>;
@@ -556,7 +556,7 @@
 				>;
 			};
 
-			sdio_cfg_func: sdio_cfg_func {
+			sdio_cfg_func: sdio-cfg-pins {
 				pinctrl-single,pins = <
 					0x004 0x0 /* SDIO_CMD */
 					0x008 0x0 /* SDIO_DATA0 */
@@ -592,7 +592,7 @@
 			/* pin base, nr pins & gpio function */
 			pinctrl-single,gpio-range = <&range 0 12 0>;
 
-			sd_pmx_func: sd_pmx_func {
+			sd_pmx_func: sd-pins {
 				pinctrl-single,pins = <
 					0x000 MUX_M1 /* SD_CLK */
 					0x004 MUX_M1 /* SD_CMD */
@@ -610,7 +610,7 @@
 			#pinctrl-cells = <1>;
 			pinctrl-single,register-width = <0x20>;
 
-			sd_clk_cfg_func: sd_clk_cfg_func {
+			sd_clk_cfg_func: sd-clk-cfg-pins {
 				pinctrl-single,pins = <
 					0x000 0x0 /* SD_CLK */
 				>;
@@ -632,7 +632,7 @@
 				>;
 			};
 
-			sd_cfg_func: sd_cfg_func {
+			sd_cfg_func: sd-cfg-pins {
 				pinctrl-single,pins = <
 					0x004 0x0 /* SD_CMD */
 					0x008 0x0 /* SD_DATA0 */
@@ -665,7 +665,7 @@
 			#pinctrl-cells = <1>;
 			pinctrl-single,register-width = <0x20>;
 
-			pwr_key_cfg_func: pwr_key_cfg_func {
+			pwr_key_cfg_func: pwr-key-cfg-pins {
 				pinctrl-single,pins = <
 					0x090 0x0 /* GPIO_203 */
 				>;
@@ -686,7 +686,7 @@
 				>;
 			};
 
-			usb_cfg_func: usb_cfg_func {
+			usb_cfg_func: usb-cfg-pins {
 				pinctrl-single,pins = <
 					0x0AC 0x0 /* GPIO_221 */
 				>;
@@ -707,7 +707,7 @@
 				>;
 			};
 
-			spi0_cfg_func: spi0_cfg_func {
+			spi0_cfg_func: spi0-cfg-pins {
 				pinctrl-single,pins = <
 					0x0c8 0x0 /* SPI0_DI */
 					0x0cc 0x0 /* SPI0_DO */
@@ -730,7 +730,7 @@
 				>;
 			};
 
-			spi2_cfg_func: spi2_cfg_func {
+			spi2_cfg_func: spi2-cfg-pins {
 				pinctrl-single,pins = <
 					0x714 0x0 /* SPI2_DI */
 					0x718 0x0 /* SPI2_DO */
@@ -753,7 +753,7 @@
 				>;
 			};
 
-			spi3_cfg_func: spi3_cfg_func {
+			spi3_cfg_func: spi3-cfg-pins {
 				pinctrl-single,pins = <
 					0x730 0x0 /* SPI3_DI */
 					0x734 0x0 /* SPI3_DO */
@@ -776,7 +776,7 @@
 				>;
 			};
 
-			spi0_clk_cfg_func: spi0_clk_cfg_func {
+			spi0_clk_cfg_func: spi0-clk-cfg-pins {
 				pinctrl-single,pins = <
 					0x0c4 0x0 /* SPI0_CLK */
 				>;
@@ -797,7 +797,7 @@
 				>;
 			};
 
-			spi2_clk_cfg_func: spi2_clk_cfg_func {
+			spi2_clk_cfg_func: spi2-clk-cfg-pins {
 				pinctrl-single,pins = <
 					0x710 0x0 /* SPI2_CLK */
 				>;
@@ -818,7 +818,7 @@
 				>;
 			};
 
-			spi3_clk_cfg_func: spi3_clk_cfg_func {
+			spi3_clk_cfg_func: spi3-clk-cfg-pins {
 				pinctrl-single,pins = <
 					0x72c 0x0 /* SPI3_CLK */
 				>;
@@ -839,7 +839,7 @@
 				>;
 			};
 
-			i2c0_cfg_func: i2c0_cfg_func {
+			i2c0_cfg_func: i2c0-cfg-pins {
 				pinctrl-single,pins = <
 					0x04c 0x0 /* I2C0_SCL */
 					0x050 0x0 /* I2C0_SDA */
@@ -861,7 +861,7 @@
 				>;
 			};
 
-			i2c1_cfg_func: i2c1_cfg_func {
+			i2c1_cfg_func: i2c1-cfg-pins {
 				pinctrl-single,pins = <
 					0x054 0x0 /* I2C1_SCL */
 					0x058 0x0 /* I2C1_SDA */
@@ -883,7 +883,7 @@
 				>;
 			};
 
-			i2c2_cfg_func: i2c2_cfg_func {
+			i2c2_cfg_func: i2c2-cfg-pins {
 				pinctrl-single,pins = <
 					0x05c 0x0 /* I2C2_SCL */
 					0x060 0x0 /* I2C2_SDA */
@@ -905,7 +905,7 @@
 				>;
 			};
 
-			pcie_clkreq_cfg_func: pcie_clkreq_cfg_func {
+			pcie_clkreq_cfg_func: pcie-clkreq-cfg-pins {
 				pinctrl-single,pins = <
 					0x0b0 0x0
 				>;
@@ -925,7 +925,7 @@
 					DRIVE7_06MA DRIVE6_MASK
 				>;
 			};
-			i2s2_cfg_func: i2s2_cfg_func {
+			i2s2_cfg_func: i2s2-cfg-pins {
 				pinctrl-single,pins = <
 					0x07c 0x0 /* I2S2_DI */
 					0x080 0x0 /* I2S2_DO */
@@ -949,7 +949,7 @@
 				>;
 			};
 
-			gpio185_cfg_func: gpio185_cfg_func {
+			gpio185_cfg_func: gpio185-cfg-pins {
 				pinctrl-single,pins = <0x048  0>;
 				pinctrl-single,bias-pulldown = <0 2 0 2>;
 				pinctrl-single,bias-pullup = <0 1 0 1>;
@@ -957,7 +957,7 @@
 				pinctrl-single,slew-rate = <0x0 0x80>;
 			};
 
-			gpio185_cfg_idle: gpio185_cfg_idle {
+			gpio185_cfg_idle: gpio185-cfg-idle-pins {
 				pinctrl-single,pins = <0x048  0>;
 				pinctrl-single,bias-pulldown = <2 2 0 2>;
 				pinctrl-single,bias-pullup = <0 1 0 1>;