diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2022-08-02 18:15:25 +0300 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2022-08-02 18:15:25 +0300 |
| commit | 3976d758e045ed0485e0e665fb3b6692572576d7 (patch) | |
| tree | 11918dfab24b4daa98293d49dc089809b5dd6e92 /arch/arm64/boot/dts/freescale | |
| parent | 47b62edcd4eb70ccf4ecfacaf1a960eecfd3f891 (diff) | |
| parent | 47d8f8b78b9b42e9817feeb75bbf758f2a3cbff8 (diff) | |
| download | linux-3976d758e045ed0485e0e665fb3b6692572576d7.tar.xz | |
Merge tag 'arm-dt-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM DT updates from Arnd Bergmann:
"As usual, the bulk of the changes for the SoC tree are devicetree file
updates, and most of these changes are for 64-bit embedded machines.
As before, there are a ton of style cleanups, and additional hardware
support for existing machines.
Looking only at the new SoC, the notable additions are:
- A whole family of Broadcom broadband SoCs, both 32-bit and 64-bit:
BCM63178, BCM63158, BCM4912, BCM6858, BCM6878, BCM6846, BCM63146,
BCM6856, BCM6855, BCM6756, BCM63148, and BCM6813. Each SoC comes
with a corresponding reference board.
- The new NXP i.MX93 SoC, the follow-up to the popular i.MX6 and
i.MX8 embedded SoCs, now using Cortex-A55 cores and the Ethos-U65
NPU.
- Qualcomm Snapdragon 8cx Gen3 (SC8280XP), the current high end of
Arm based Laptop SoCs, and its automotive cousin, the SA8540P. The
SC8280XP is used in the Lenovo Thinkpad X13s laptop that also gets
added here in addition to the reference boards.
- Allwinner H616, a newer version of the H6 SoC, targeted at
Set-top-box applications. It comes with dts files for the Orange Pi
zero2 single-board computer and the X96 Mate set-top-box
- Marvell Prestera 98DX2530 (AlleyCat5), a network switch chip in the
Armada SoC family based on the Cortex-A55 core.
New machines based on previously supported SoCs include:
- Several new machines on NXP i.MX platforms: multiple Toradex
Colibri boards using the "Iris" and "Ixora" carriers, DH
electronics i.MX8M Plus DHCOM and PDK2, TQ-Systems TQMa8MPQL, and
phytech phyBOARD-Polis-i.MX8MM.
- Google Chameleon v3 FPGA board based on Intel Arria10 and Stratix
10 Software Virtual platform, both in the SoCFPGA platform.
- Two new wireless devices based on Broadcom SoCs: The Asus GT-AX6000
Router and the Cisco Meraki MR26 access point
- Improved Chromebook support for both the Mediatek and Qualcomm SoC
families brought added machines: Acer Chromebook 514 (MT8192), Acer
Chromebook Spin 513 (MT8195) and a couple of SC7180 based machines
including the Lenovo IdeaPad Chromebook Duet 3.
- Xiaomi Mi Mix2s, LG G7 and LG V35 are mobile phones based on
Qualcomm SDM845, while Mi 5s Plus is based on MSM8996.
- Finally, there are a few development board on other chips: PCB8309
(Microchip lan966x), Radxa Rock Pi S (Rockchips RK3308) DH DRC
Compact (ST STM32MP1) and Inforce IFC6560 (Qualcomm SDM660)"
* tag 'arm-dt-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (829 commits)
dt-bindings: soc: bcm: use absolute path to other schema
dt-bindings: soc: bcm: drop quotes when not needed
dt-bindings: soc: microchip: use absolute path to other schema
dt-bindings: soc: microchip: drop quotes when not needed
ARM: dts: lan966x: keep lan966 entries alphabetically sorted
ARM: dts: lan966x: add support for pcb8309
dt-bindings: arm: at91: add lan966 pcb8309 board
ARM: dts: lan966x: Enable network driver on pcb8291
ARM: dts: lan966x: Disable can0 on pcb8291
ARM: dts: lan966x: Add gpio-restart
dt-bindings: arm: aspeed: add Aspeed Evaluation boards
arm64: dts: qcom: Add support for Xiaomi Mi Mix2s
dt-bindings: arm: qcom: Add Xiaomi Mi Mix2s bindings
dt-bindings: arm: qcom: Document lg,judyln and lg,judyp devices
dt-bindings: arm: qcom: add missing SM6350 board compatibles
dt-bindings: arm: qcom: add missing SM6125 board compatibles
dt-bindings: arm: qcom: add missing SDM845 board compatibles
dt-bindings: arm: qcom: add missing SDM636 board compatibles
dt-bindings: arm: qcom: add missing SDM630 board compatibles
dt-bindings: arm: qcom: add missing QCS404 board compatibles
...
Diffstat (limited to 'arch/arm64/boot/dts/freescale')
53 files changed, 4550 insertions, 172 deletions
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 238a83e5b8c6..8bf7f7ecebaa 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -58,6 +58,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-mx8menlo.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-rdk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb @@ -79,9 +80,11 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dev.dtb @@ -107,6 +110,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-imx219.dtbo imx8mm-venice-gw72xx-0x-rs232-rts-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs232-rts.dtbo diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts index e22c5e77fecd..5a8d85a7d161 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts @@ -69,7 +69,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "n25q128a11", "jedec,spi-nor"; + compatible = "micron,n25q128a11", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <10000000>; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index 50a72cda4727..a863022529ac 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -204,7 +204,7 @@ compatible = "fsl,sec-v5.4-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; + reg = <0x10000 0x10000>; interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; }; @@ -212,7 +212,7 @@ compatible = "fsl,sec-v5.4-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; + reg = <0x20000 0x10000>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; }; @@ -220,7 +220,7 @@ compatible = "fsl,sec-v5.4-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; + reg = <0x30000 0x10000>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; }; @@ -228,7 +228,7 @@ compatible = "fsl,sec-v5.4-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; + reg = <0x40000 0x10000>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; }; @@ -271,6 +271,14 @@ }; }; + sfp: efuse@1e80000 { + compatible = "fsl,ls1021a-sfp"; + reg = <0x0 0x1e80000 0x0 0x10000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; + clock-names = "sfp"; + }; + sec_mon: sec_mon@1e90000 { compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon"; @@ -465,7 +473,7 @@ status = "disabled"; }; - edma0: edma@2c00000 { + edma0: dma-controller@2c00000 { #dma-cells = <2>; compatible = "fsl,vf610-edma"; reg = <0x0 0x2c00000 0x0 0x10000>, diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts index 5baf060acf93..0bb2f28a0441 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts @@ -93,7 +93,7 @@ compatible = "mdio-mux-multiplexer"; mux-controls = <&mux 0>; mdio-parent-bus = <&enetc_mdio_pf3>; - #address-cells=<1>; + #address-cells = <1>; #size-cells = <0>; /* on-board RGMII PHY */ diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index d5cdd77e5a95..5627dd7734f3 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -96,7 +96,7 @@ }; reboot { - compatible ="syscon-reboot"; + compatible = "syscon-reboot"; regmap = <&rst>; offset = <0>; mask = <0x02>; @@ -120,13 +120,13 @@ }; gic: interrupt-controller@6000000 { - compatible= "arm,gic-v3"; + compatible = "arm,gic-v3"; #address-cells = <2>; #size-cells = <2>; ranges; - reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ - #interrupt-cells= <3>; + #interrupt-cells = <3>; interrupt-controller; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>; @@ -772,28 +772,28 @@ sec_jr0: jr@10000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; + reg = <0x10000 0x10000>; interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; }; sec_jr1: jr@20000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; + reg = <0x20000 0x10000>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; }; sec_jr2: jr@30000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; + reg = <0x30000 0x10000>; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; }; sec_jr3: jr@40000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; + reg = <0x40000 0x10000>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 21200cbf7161..ca3d5a90d6d4 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -144,7 +144,7 @@ }; reboot { - compatible ="syscon-reboot"; + compatible = "syscon-reboot"; regmap = <&dcfg>; offset = <0xb0>; mask = <0x02>; @@ -354,7 +354,7 @@ compatible = "fsl,sec-v5.4-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; + reg = <0x10000 0x10000>; interrupts = <0 71 0x4>; }; @@ -362,7 +362,7 @@ compatible = "fsl,sec-v5.4-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; + reg = <0x20000 0x10000>; interrupts = <0 72 0x4>; }; @@ -370,7 +370,7 @@ compatible = "fsl,sec-v5.4-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; + reg = <0x30000 0x10000>; interrupts = <0 73 0x4>; }; @@ -378,11 +378,19 @@ compatible = "fsl,sec-v5.4-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; + reg = <0x40000 0x10000>; interrupts = <0 74 0x4>; }; }; + sfp: efuse@1e80000 { + compatible = "fsl,ls1021a-sfp"; + reg = <0x0 0x1e80000 0x0 0x10000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; + clock-names = "sfp"; + }; + dcfg: dcfg@1ee0000 { compatible = "fsl,ls1043a-dcfg", "syscon"; reg = <0x0 0x1ee0000 0x0 0x10000>; @@ -784,7 +792,7 @@ big-endian; }; - edma0: edma@2c00000 { + edma0: dma-controller@2c00000 { #dma-cells = <2>; compatible = "fsl,vf610-edma"; reg = <0x0 0x2c00000 0x0 0x10000>, diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 0085e83adf65..feab604322cf 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -112,7 +112,7 @@ }; reboot { - compatible ="syscon-reboot"; + compatible = "syscon-reboot"; regmap = <&dcfg>; offset = <0xb0>; mask = <0x02>; @@ -360,7 +360,7 @@ compatible = "fsl,sec-v5.4-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; + reg = <0x10000 0x10000>; interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; }; @@ -368,7 +368,7 @@ compatible = "fsl,sec-v5.4-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; + reg = <0x20000 0x10000>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; }; @@ -376,7 +376,7 @@ compatible = "fsl,sec-v5.4-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; + reg = <0x30000 0x10000>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; }; @@ -384,7 +384,7 @@ compatible = "fsl,sec-v5.4-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; + reg = <0x40000 0x10000>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -413,6 +413,14 @@ ranges = <0x0 0x5 0x08000000 0x8000000>; }; + sfp: efuse@1e80000 { + compatible = "fsl,ls1021a-sfp"; + reg = <0x0 0x1e80000 0x0 0x10000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; + clock-names = "sfp"; + }; + dcfg: dcfg@1ee0000 { compatible = "fsl,ls1046a-dcfg", "syscon"; reg = <0x0 0x1ee0000 0x0 0x1000>; @@ -683,7 +691,7 @@ big-endian; }; - edma0: edma@2c00000 { + edma0: dma-controller@2c00000 { #dma-cells = <2>; compatible = "fsl,vf610-edma"; reg = <0x0 0x2c00000 0x0 0x10000>, diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts index d3f03dcbb8c3..ef6c8967533e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts @@ -35,14 +35,14 @@ * external power off (e.g ATX Power Button) * asserted */ - powerdn { + button-powerdn { label = "External Power Down"; gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; }; /* Rear Panel 'ADMIN' button (GPIO_H) */ - admin { + button-admin { label = "ADMIN button"; gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; linux,code = <KEY_WPS_BUTTON>; @@ -52,17 +52,17 @@ leds { compatible = "gpio-leds"; - sfp1down { + led-0 { label = "ten64:green:sfp1:down"; gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; }; - sfp2up { + led-1 { label = "ten64:green:sfp2:up"; gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; }; - admin { + led-2 { label = "ten64:admin"; gpios = <&sfpgpio 12 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index f476b7d8b056..421d879013d7 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -269,6 +269,14 @@ }; }; + sfp: efuse@1e80000 { + compatible = "fsl,ls1028a-sfp"; + reg = <0x0 0x1e80000 0x0 0x10000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; + clock-names = "sfp"; + }; + tmu: tmu@1f80000 { compatible = "fsl,qoriq-tmu"; reg = <0x0 0x1f80000 0x0 0x10000>; @@ -526,28 +534,28 @@ sec_jr0: jr@10000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; + reg = <0x10000 0x10000>; interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; }; sec_jr1: jr@20000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; + reg = <0x20000 0x10000>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; }; sec_jr2: jr@30000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; + reg = <0x30000 0x10000>; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; }; sec_jr3: jr@40000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; + reg = <0x40000 0x10000>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 4ba1e0499dfd..d76f1c42f3fa 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -73,7 +73,7 @@ }; reboot { - compatible ="syscon-reboot"; + compatible = "syscon-reboot"; regmap = <&rstcr>; offset = <0x0>; mask = <0x2>; @@ -278,6 +278,14 @@ little-endian; }; + sfp: efuse@1e80000 { + compatible = "fsl,ls1028a-sfp"; + reg = <0x0 0x1e80000 0x0 0x10000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; + clock-names = "sfp"; + }; + isc: syscon@1f70000 { compatible = "fsl,ls2080a-isc", "syscon"; reg = <0x0 0x1f70000 0x0 0x10000>; @@ -479,28 +487,28 @@ sec_jr0: jr@10000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; + reg = <0x10000 0x10000>; interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; }; sec_jr1: jr@20000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; + reg = <0x20000 0x10000>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; }; sec_jr2: jr@30000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; + reg = <0x30000 0x10000>; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; }; sec_jr3: jr@40000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; + reg = <0x40000 0x10000>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts index 2ecfa90f5e28..4d721197d837 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts @@ -36,7 +36,7 @@ compatible = "mdio-mux-multiplexer"; mux-controls = <&mux 0>; mdio-parent-bus = <&emdio1>; - #address-cells=<1>; + #address-cells = <1>; #size-cells = <0>; mdio@0 { /* On-board PHY #1 RGMI1*/ @@ -104,7 +104,7 @@ compatible = "mdio-mux-multiplexer"; mux-controls = <&mux 1>; mdio-parent-bus = <&emdio2>; - #address-cells=<1>; + #address-cells = <1>; #size-cells = <0>; mdio@0 { /* Slot #1 (secondary EMI) */ diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 47ea854720ce..6680fb2a6dc9 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -632,28 +632,28 @@ sec_jr0: jr@10000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; + reg = <0x10000 0x10000>; interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; }; sec_jr1: jr@20000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; + reg = <0x20000 0x10000>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; }; sec_jr2: jr@30000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; + reg = <0x30000 0x10000>; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; }; sec_jr3: jr@40000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; + reg = <0x40000 0x10000>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -671,6 +671,14 @@ little-endian; }; + sfp: efuse@1e80000 { + compatible = "fsl,ls1028a-sfp"; + reg = <0x0 0x1e80000 0x0 0x10000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; + clock-names = "sfp"; + }; + isc: syscon@1f70000 { compatible = "fsl,lx2160a-isc", "syscon"; reg = <0x0 0x1f70000 0x0 0x10000>; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts index a1644ceed154..9f5ff1ffe7d5 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts @@ -34,7 +34,7 @@ compatible = "mdio-mux-multiplexer"; mux-controls = <&mux 0>; mdio-parent-bus = <&emdio1>; - #address-cells=<1>; + #address-cells = <1>; #size-cells = <0>; mdio@0 { /* On-board RTL8211F PHY #1 RGMII1 */ @@ -114,7 +114,7 @@ compatible = "mdio-mux-multiplexer"; mux-controls = <&mux 1>; mdio-parent-bus = <&emdio2>; - #address-cells=<1>; + #address-cells = <1>; #size-cells = <0>; mdio@0 { /* Slot #1 (secondary EMI) */ diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index a79f42a9618e..82a1c4488378 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -54,7 +54,7 @@ conn_subsys: bus@5b000000 { clock-names = "ipg", "per", "ahb"; power-domains = <&pd IMX_SC_R_SDHC_1>; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; status = "disabled"; }; @@ -83,8 +83,8 @@ conn_subsys: bus@5b000000 { assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; assigned-clock-rates = <250000000>, <125000000>; - fsl,num-tx-queues=<3>; - fsl,num-rx-queues=<3>; + fsl,num-tx-queues = <3>; + fsl,num-rx-queues = <3>; power-domains = <&pd IMX_SC_R_ENET_0>; status = "disabled"; }; @@ -103,8 +103,8 @@ conn_subsys: bus@5b000000 { assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>; assigned-clock-rates = <250000000>, <125000000>; - fsl,num-tx-queues=<3>; - fsl,num-rx-queues=<3>; + fsl,num-tx-queues = <3>; + fsl,num-rx-queues = <3>; power-domains = <&pd IMX_SC_R_ENET_1>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi index f338a886d811..03266bd90a06 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi @@ -285,14 +285,14 @@ &usbotg1 { vbus-supply = <®_usbotg1>; disable-over-current; - dr_mode="otg"; + dr_mode = "otg"; status = "okay"; }; &usbotg2 { pinctrl-names = "default"; disable-over-current; - dr_mode="host"; + dr_mode = "host"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index c42b966f7a64..7d6317d95b13 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -75,6 +75,11 @@ linux,autosuspend-period = <125>; }; + audio_codec_bt_sco: audio-codec-bt-sco { + compatible = "linux,bt-sco"; + #sound-dai-cells = <1>; + }; + wm8524: audio-codec { #sound-dai-cells = <0>; compatible = "wlf,wm8524"; @@ -83,6 +88,25 @@ wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; }; + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai2>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&audio_codec_bt_sco 1>; + }; + }; + sound-wm8524 { compatible = "simple-audio-card"; simple-audio-card,name = "wm8524-audio"; @@ -346,6 +370,16 @@ status = "okay"; }; +&sai2 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clk IMX8MM_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; @@ -494,6 +528,15 @@ >; }; + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 + >; + }; + pinctrl_sai3: sai3grp { fsl,pins = < MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi index b40148d728ea..9e6170d9394e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi @@ -84,42 +84,42 @@ }; reg_buck1: buck1 { - regulator-min-microvolt = <400000>; + regulator-min-microvolt = <400000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; reg_buck2: buck2 { - regulator-min-microvolt = <400000>; + regulator-min-microvolt = <400000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; reg_buck3: buck3 { - regulator-min-microvolt = <400000>; + regulator-min-microvolt = <400000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; reg_buck4: buck4 { - regulator-min-microvolt = <400000>; + regulator-min-microvolt = <400000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; reg_buck5: buck5 { - regulator-min-microvolt = <400000>; + regulator-min-microvolt = <400000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; reg_buck6: buck6 { - regulator-min-microvolt = <400000>; + regulator-min-microvolt = <400000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts b/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts index 92eaf4ef4563..c97f4e06ae5f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts @@ -20,13 +20,13 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_led>; - user1 { + led-1 { label = "TestLed601"; gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; }; - user2 { + led-2 { label = "TestLed602"; gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts new file mode 100644 index 000000000000..4a3df2b77b0b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts @@ -0,0 +1,450 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet <t.remmet@phytec.de> + */ + +/dts-v1/; + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/phy/phy-imx8-pcie.h> +#include "imx8mm-phycore-som.dtsi" + +/ { + model = "PHYTEC phyBOARD-Polis-i.MX8MM RDK"; + compatible = "phytec,imx8mm-phyboard-polis-rdk", + "phytec,imx8mm-phycore-som", "fsl,imx8mm"; + + chosen { + stdout-path = &uart3; + }; + + bt_osc_32k: bt-lp-clock { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "bt_osc_32k"; + #clock-cells = <0>; + }; + + can_osc_40m: can-clock { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + clock-output-names = "can_osc_40m"; + #clock-cells = <0>; + }; + + fan { + compatible = "gpio-fan"; + gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0 + 13000 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fan>; + #cooling-cells = <2>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-0 { + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_DISK; + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc2"; + }; + + led-1 { + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_DISK; + gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + }; + + led-2 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_CPU; + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + usdhc1_pwrseq: pwr-seq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <60>; + reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; + }; + + reg_can_en: regulator-can-en { + compatible = "regulator-fixed"; + gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_en>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "CAN_EN"; + startup-delay-us = <20>; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1 { + compatible = "regulator-fixed"; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1pwrgrp>; + regulator-name = "usb_otg1_vbus"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <20000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VSD_3V3"; + }; + + reg_vcc_3v3: regulator-vcc-3v3 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VCC_3V3"; + }; +}; + +/* SPI - CAN MCP251XFD */ +&ecspi1 { + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + can0: can@0 { + compatible = "microchip,mcp251xfd"; + clocks = <&can_osc_40m>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_int>; + reg = <0>; + spi-max-frequency = <20000000>; + xceiver-supply = <®_can_en>; + }; +}; + +&gpio1 { + gpio-line-names = "nINT_ETHPHY", "LED_RED", "WDOG_INT", "X_RTC_INT", + "", "", "", "RESET_ETHPHY", + "CAN_nINT", "CAN_EN", "nENABLE_FLATLINK", "", + "USB_OTG_VBUS_EN", "", "LED_GREEN", "LED_BLUE"; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", + "", "", "BT_REG_ON", "WL_REG_ON", + "BT_DEV_WAKE", "BT_HOST_WAKE", "", "", + "X_SD2_CD_B", "", "", "", + "", "", "", "SD2_RESET_B"; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", + "", "", "", "", + "FAN", "miniPCIe_nPERST", "", "", + "COEX1", "COEX2"; +}; + +&gpio5 { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "ECSPI1_SS0"; +}; + +/* PCIe */ +&pcie0 { + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + assigned-clock-rates = <10000000>, <250000000>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_PHY>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie_phy { + clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; + fsl,tx-deemph-gen1 = <0x2d>; + fsl,tx-deemph-gen2 = <0xf>; + status = "okay"; +}; + +&rv3028 { + trickle-resistor-ohms = <3000>; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +/* UART - RS232/RS485 */ +&uart1 { + assigned-clocks = <&clk IMX8MM_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "okay"; +}; + +/* UART - Sterling-LWB Bluetooth */ +&uart2 { + assigned-clocks = <&clk IMX8MM_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + fsl,dte-mode; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_bt>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&bt_osc_32k>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + interrupt-names = "host-wakeup"; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_EDGE_BOTH>; + max-speed = <2000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt>; + shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; + vddio-supply = <®_vcc_3v3>; + }; +}; + +/* UART - console */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +/* USB */ +&usbotg1 { + adp-disable; + dr_mode = "otg"; + over-current-active-low; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + srp-disable; + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; +}; + +/* SDIO - Sterling-LWB Wifi */ +&usdhc1 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC1>; + assigned-clock-rates = <200000000>; + bus-width = <4>; + mmc-pwrseq = <&usdhc1_pwrseq>; + non-removable; + no-1-8-v; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; +}; + +/* SD-Card */ +&usdhc2 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; + assigned-clock-rates = <200000000>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <®_nvcc_sd2>; + status = "okay"; +}; + +&iomuxc { + pinctrl_bt: btgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00 + MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00 + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00 + >; + }; + + pinctrl_can_en: can-engrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00 + >; + }; + + pinctrl_can_int: can-intgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x80 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x80 + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x80 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00 + >; + }; + + pinctrl_fan: fan0grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x16 + >; + }; + + pinctrl_leds: leds1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16 + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16 + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x00 + MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12 + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x12 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x00 + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x00 + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x00 + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x00 + >; + }; + + pinctrl_uart2_bt: uart2btgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x00 + MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x00 + MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x00 + MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x00 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40 + >; + }; + + pinctrl_usbotg1pwrgrp: usbotg1pwrgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x00 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi new file mode 100644 index 000000000000..995b44efb1b6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi @@ -0,0 +1,440 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet <t.remmet@phytec.de> + */ + +#include "imx8mm.dtsi" +#include <dt-bindings/net/ti-dp83867.h> + +/ { + model = "PHYTEC phyCORE-i.MX8MM"; + compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm"; + + aliases { + rtc0 = &rv3028; + rtc1 = &snvs_rtc; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + reg_vdd_3v3_s: regulator-vdd-3v3-s { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VDD_3V3_S"; + }; +}; + +&A53_0 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_1 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_2 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_3 { + cpu-supply = <®_vdd_arm>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; +}; + +/* Ethernet */ +&fec1 { + fsl,magic-packet; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + enet-phy-lane-no-swap; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + reg = <0>; + reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + }; + }; +}; + +/* SPI Flash */ +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + som_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&gpio1 { + gpio-line-names = "nINT_ETHPHY", "", "WDOG_INT", "X_RTC_INT", + "", "", "", "RESET_ETHPHY", + "", "", "nENABLE_FLATLINK"; +}; + +/* I2C1 */ +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default","gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic@8 { + compatible = "nxp,pf8121a"; + reg = <0x08>; + + regulators { + reg_nvcc_sd1: ldo1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "NVCC_SD1 (LDO1)"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_nvcc_sd2: ldo2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "NVCC_SD2 (LDO2)"; + vselect-en; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_vcc_enet: ldo3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2500000>; + regulator-min-microvolt = <1500000>; + regulator-name = "VCC_ENET_2V5 (LDO3)"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_vdda_1v8: ldo4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1500000>; + regulator-name = "VDDA_1V8 (LDO4)"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-min-microvolt = <1500000>; + regulator-suspend-max-microvolt = <1500000>; + }; + }; + + reg_soc_vdda_phy: buck1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <400000>; + regulator-name = "VDD_SOC_VDDA_PHY_0P8 (BUCK1)"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-min-microvolt = <400000>; + regulator-suspend-max-microvolt = <400000>; + }; + }; + + reg_vdd_gpu_dram: buck2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <1000000>; + regulator-name = "VDD_GPU_DRAM (BUCK2)"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1000000>; + regulator-suspend-min-microvolt = <1000000>; + }; + }; + + reg_vdd_gpu: buck3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <400000>; + regulator-name = "VDD_VPU (BUCK3)"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_vdd_mipi: buck4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1050000>; + regulator-min-microvolt = <900000>; + regulator-name = "VDD_MIPI_0P9 (BUCK4)"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_vdd_arm: buck5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1050000>; + regulator-min-microvolt = <400000>; + regulator-name = "VDD_ARM (BUCK5)"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_vdd_1v8: buck6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "VDD_1V8 (BUCK6)"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1800000>; + regulator-suspend-min-microvolt = <1800000>; + }; + }; + + reg_nvcc_dram: buck7 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1100000>; + regulator-name = "NVCC_DRAM_1P1V (BUCK7)"; + }; + + reg_vsnvs: vsnvs { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "NVCC_SNVS_1P8 (VSNVS)"; + }; + }; + }; + + sn65dsi83: bridge@2d { + compatible = "ti,sn65dsi83"; + enable-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sn65dsi83>; + reg = <0x2d>; + status = "disabled"; + }; + + eeprom@51 { + compatible = "atmel,24c32"; + pagesize = <32>; + reg = <0x51>; + vcc-supply = <®_vdd_3v3_s>; + }; + + rv3028: rtc@52 { + compatible = "microcrystal,rv3028"; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + reg = <0x52>; + }; +}; + +/* EMMC */ +&usdhc3 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + keep-power-in-suspend; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + non-removable; + status = "okay"; +}; + +/* Watchdog */ +&wdog1 { + fsl,ext-reset-output; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + status = "okay"; +}; + +&iomuxc { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x2 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x2 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90 + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90 + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90 + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16 + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16 + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16 + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x10 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c0 + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c0 + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1e0 + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1e0 + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 + >; + }; + + pinctrl_sn65dsi83: sn65dsi83grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x26 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts index ac1fe1530ac7..d643381417f1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts @@ -36,19 +36,19 @@ gpio-keys { compatible = "gpio-keys"; - back { + key-back { label = "Back"; gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; linux,code = <KEY_BACK>; }; - home { + key-home { label = "Home"; gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; linux,code = <KEY_HOME>; }; - menu { + key-menu { label = "Menu"; gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; linux,code = <KEY_MENU>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi index 00f86cada30d..66a0d103c90f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi @@ -16,13 +16,13 @@ gpio-keys { compatible = "gpio-keys"; - user-pb { + key-user-pb { label = "user_pb"; gpios = <&gpio 2 GPIO_ACTIVE_LOW>; linux,code = <BTN_0>; }; - user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = <BTN_1>; interrupt-parent = <&gsc>; @@ -36,14 +36,14 @@ interrupts = <1>; }; - eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = <BTN_3>; interrupt-parent = <&gsc>; interrupts = <2>; }; - tamper { + key-tamper { label = "tamper"; linux,code = <BTN_4>; interrupt-parent = <&gsc>; @@ -286,8 +286,8 @@ regulator-name = "buck1"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1000000>; - regulator-min-microamp = <3800000>; - regulator-max-microamp = <6800000>; + regulator-min-microamp = <3800000>; + regulator-max-microamp = <6800000>; regulator-boot-on; regulator-always-on; }; @@ -297,8 +297,8 @@ regulator-name = "buck2"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <900000>; - regulator-min-microamp = <2200000>; - regulator-max-microamp = <5200000>; + regulator-min-microamp = <2200000>; + regulator-max-microamp = <5200000>; regulator-boot-on; regulator-always-on; }; @@ -308,8 +308,8 @@ regulator-name = "buck3"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1000000>; - regulator-min-microamp = <3800000>; - regulator-max-microamp = <6800000>; + regulator-min-microamp = <3800000>; + regulator-max-microamp = <6800000>; regulator-always-on; }; @@ -318,8 +318,8 @@ regulator-name = "buck4"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-min-microamp = <2200000>; - regulator-max-microamp = <5200000>; + regulator-min-microamp = <2200000>; + regulator-max-microamp = <5200000>; regulator-boot-on; regulator-always-on; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts index 24737e89038a..35fb929e7bcc 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts @@ -38,13 +38,13 @@ gpio-keys { compatible = "gpio-keys"; - user-pb { + key-user-pb { label = "user_pb"; gpios = <&gpio 2 GPIO_ACTIVE_LOW>; linux,code = <BTN_0>; }; - user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = <BTN_1>; interrupt-parent = <&gsc>; @@ -58,14 +58,14 @@ interrupts = <1>; }; - eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = <BTN_3>; interrupt-parent = <&gsc>; interrupts = <2>; }; - tamper { + key-tamper { label = "tamper"; linux,code = <BTN_4>; interrupt-parent = <&gsc>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index 407ab4592b4c..6dc5eda2d256 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts @@ -42,13 +42,13 @@ gpio-keys { compatible = "gpio-keys"; - user-pb { + key-user-pb { label = "user_pb"; gpios = <&gpio 2 GPIO_ACTIVE_LOW>; linux,code = <BTN_0>; }; - user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = <BTN_1>; interrupt-parent = <&gsc>; @@ -62,14 +62,14 @@ interrupts = <1>; }; - eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = <BTN_3>; interrupt-parent = <&gsc>; interrupts = <2>; }; - tamper { + key-tamper { label = "tamper"; linux,code = <BTN_4>; interrupt-parent = <&gsc>; @@ -651,7 +651,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; - cts-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + cts-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts index a7dae9bd4c11..a65761a53f23 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts @@ -33,13 +33,13 @@ gpio-keys { compatible = "gpio-keys"; - user-pb { + key-user-pb { label = "user_pb"; gpios = <&gpio 2 GPIO_ACTIVE_LOW>; linux,code = <BTN_0>; }; - user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = <BTN_1>; interrupt-parent = <&gsc>; @@ -53,7 +53,7 @@ interrupts = <1>; }; - eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = <BTN_3>; interrupt-parent = <&gsc>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index eafa88d980b3..d1b4582f44c4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -43,7 +43,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - wakeup { + key-wakeup { debounce-interval = <10>; /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; @@ -154,6 +154,14 @@ cpu-supply = <®_vdd_arm>; }; +&cpu_alert0 { + temperature = <95000>; +}; + +&cpu_crit0 { + temperature = <105000>; +}; + &ddrc { operating-points-v2 = <&ddrc_opp_table>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 1bf070473829..afb90f59c83c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -212,7 +212,7 @@ clk_ext4: clock-ext4 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency= <133000000>; + clock-frequency = <133000000>; clock-output-names = "clk_ext4"; }; @@ -287,7 +287,7 @@ clock-names = "main_clk"; }; - soc@0 { + soc: soc@0 { compatible = "fsl,imx8mm-soc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -602,6 +602,11 @@ wakeup-source; status = "disabled"; }; + + snvs_lpgpr: snvs-lpgpr { + compatible = "fsl,imx8mm-snvs-lpgpr", + "fsl,imx7d-snvs-lpgpr"; + }; }; clk: clock-controller@30380000 { @@ -911,6 +916,7 @@ compatible = "fsl,sec-v4.0-job-ring"; reg = <0x1000 0x1000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; }; sec_jr1: jr@2000 { @@ -995,7 +1001,7 @@ <&clk IMX8MM_CLK_USDHC1_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; @@ -1009,7 +1015,7 @@ <&clk IMX8MM_CLK_USDHC2_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; @@ -1023,7 +1029,7 @@ <&clk IMX8MM_CLK_USDHC3_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi index 02f37dcda7ed..9e82069c941f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi @@ -146,7 +146,7 @@ }; &easrc { - fsl,asrc-rate = <48000>; + fsl,asrc-rate = <48000>; status = "okay"; }; @@ -182,7 +182,7 @@ &usbotg1 { vbus-supply = <®_usb_otg_vbus>; disable-over-current; - dr_mode="otg"; + dr_mode = "otg"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index d1f6cccfa00d..261c36540079 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -47,6 +47,11 @@ linux,autosuspend-period = <125>; }; + audio_codec_bt_sco: audio-codec-bt-sco { + compatible = "linux,bt-sco"; + #sound-dai-cells = <1>; + }; + wm8524: audio-codec { #sound-dai-cells = <0>; compatible = "wlf,wm8524"; @@ -57,6 +62,25 @@ clock-names = "mclk"; }; + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai2>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&audio_codec_bt_sco 1>; + }; + }; + sound-wm8524 { compatible = "fsl,imx-audio-wm8524"; model = "wm8524-audio"; @@ -78,7 +102,7 @@ }; &easrc { - fsl,asrc-rate = <48000>; + fsl,asrc-rate = <48000>; status = "okay"; }; @@ -183,6 +207,16 @@ }; }; +&sai2 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clk IMX8MN_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; @@ -354,6 +388,15 @@ >; }; + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 + >; + }; + pinctrl_sai3: sai3grp { fsl,pins = < MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts index f61c48776cf3..3ed7021a487c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts @@ -26,19 +26,19 @@ gpio-keys { compatible = "gpio-keys"; - back { + key-back { label = "Back"; gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; linux,code = <KEY_BACK>; }; - home { + key-home { label = "Home"; gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; linux,code = <KEY_HOME>; }; - menu { + key-menu { label = "Menu"; gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; linux,code = <KEY_MENU>; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts index 367a232675aa..636f8602b979 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts @@ -39,13 +39,13 @@ gpio-keys { compatible = "gpio-keys"; - user-pb { + key-user-pb { label = "user_pb"; gpios = <&gpio 2 GPIO_ACTIVE_LOW>; linux,code = <BTN_0>; }; - user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = <BTN_1>; interrupt-parent = <&gsc>; @@ -59,14 +59,14 @@ interrupts = <1>; }; - eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = <BTN_3>; interrupt-parent = <&gsc>; interrupts = <2>; }; - tamper { + key-tamper { label = "tamper"; linux,code = <BTN_4>; interrupt-parent = <&gsc>; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index e41e1d56f980..0c71b740a316 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -212,7 +212,7 @@ clk_ext4: clock-ext4 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency= <133000000>; + clock-frequency = <133000000>; clock-output-names = "clk_ext4"; }; @@ -269,7 +269,7 @@ arm,no-tick-in-suspend; }; - soc@0 { + soc: soc@0 { compatible = "fsl,imx8mn-soc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -422,7 +422,7 @@ "ctx2_rx", "ctx2_tx", "ctx3_rx", "ctx3_tx"; firmware-name = "imx/easrc/easrc-imx8mn.bin"; - fsl,asrc-rate = <8000>; + fsl,asrc-rate = <8000>; fsl,asrc-format = <2>; status = "disabled"; }; @@ -857,6 +857,7 @@ compatible = "fsl,sec-v4.0-job-ring"; reg = <0x1000 0x1000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; }; sec_jr1: jr@2000 { @@ -941,7 +942,7 @@ <&clk IMX8MN_CLK_USDHC1_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; @@ -955,7 +956,7 @@ <&clk IMX8MN_CLK_USDHC2_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; @@ -969,7 +970,7 @@ <&clk IMX8MN_CLK_USDHC3_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts new file mode 100644 index 000000000000..2ca2ede2e94e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2022 Marek Vasut <marex@denx.de> + */ + +/dts-v1/; + +#include <dt-bindings/leds/common.h> +#include <dt-bindings/net/qca-ar803x.h> +#include <dt-bindings/phy/phy-imx8-pcie.h> +#include "imx8mp-dhcom-som.dtsi" + +/ { + model = "DH electronics i.MX8M Plus DHCOM Premium Developer Kit (2)"; + compatible = "dh,imx8mp-dhcom-pdk2", "fsl,imx8mp"; + + chosen { + stdout-path = &uart1; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-0 { + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; /* GPIO A */ + label = "TA1-GPIO-A"; + linux,code = <KEY_A>; + pinctrl-0 = <&pinctrl_dhcom_a>; + pinctrl-names = "default"; + wakeup-source; + }; + + button-1 { + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; /* GPIO B */ + label = "TA2-GPIO-B"; + linux,code = <KEY_B>; + pinctrl-0 = <&pinctrl_dhcom_b>; + pinctrl-names = "default"; + wakeup-source; + }; + + button-2 { + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; /* GPIO C */ + label = "TA3-GPIO-C"; + linux,code = <KEY_C>; + pinctrl-0 = <&pinctrl_dhcom_c>; + pinctrl-names = "default"; + wakeup-source; + }; + + button-3 { + gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; /* GPIO D */ + label = "TA4-GPIO-D"; + linux,code = <KEY_D>; + pinctrl-0 = <&pinctrl_dhcom_d>; + pinctrl-names = "default"; + wakeup-source; + }; + }; + + led { + compatible = "gpio-leds"; + + led-0 { + color = <LED_COLOR_ID_GREEN>; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* GPIO E */ + pinctrl-0 = <&pinctrl_dhcom_e>; + pinctrl-names = "default"; + }; + + led-1 { + color = <LED_COLOR_ID_GREEN>; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* GPIO F */ + pinctrl-0 = <&pinctrl_dhcom_f>; + pinctrl-names = "default"; + }; + + led-2 { + color = <LED_COLOR_ID_GREEN>; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; /* GPIO H */ + pinctrl-0 = <&pinctrl_dhcom_h>; + pinctrl-names = "default"; + }; + + led-3 { + color = <LED_COLOR_ID_GREEN>; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */ + pinctrl-0 = <&pinctrl_dhcom_i>; + pinctrl-names = "default"; + }; + }; +}; + +/* + * PDK2 carrier board uses SoM with KSZ9131 populated and connected to + * SoM EQoS ethernet RGMII interface. Remove the other SoM PHY DT node. + */ +/delete-node/ ðphy0f; + +/* + * PDK2 carrier board has KSZ9021 PHY populated and connected to SoM FEC + * ethernet RGMII interface. The SoM is not populated with second FEC PHY. + */ +/delete-node/ ðphy1f; + +&fec { /* Second ethernet */ + phy-handle = <ðphypdk>; + + mdio { + ethphypdk: ethernet-phy@7 { /* KSZ 9021 */ + compatible = "ethernet-phy-ieee802.3-c22"; + pinctrl-0 = <&pinctrl_ethphy1>; + pinctrl-names = "default"; + interrupt-parent = <&gpio4>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + max-speed = <100>; + reg = <7>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + rxdv-skew-ps = <0>; + txc-skew-ps = <3000>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + txen-skew-ps = <0>; + }; + }; +}; + +&flexcan1 { + status = "okay"; +}; + +&usb3_1 { + fsl,over-current-active-low; +}; + +&iomuxc { + /* + * GPIO_A,B,C,D are connected to buttons. + * GPIO_E,F,H,I are connected to LEDs. + * GPIO_M is connected to CLKOUT2. + */ + pinctrl-0 = <&pinctrl_hog_base + &pinctrl_dhcom_g &pinctrl_dhcom_j + &pinctrl_dhcom_k &pinctrl_dhcom_l + &pinctrl_dhcom_int>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi new file mode 100644 index 000000000000..a616eb378002 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi @@ -0,0 +1,1030 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021-2022 Marek Vasut <marex@denx.de> + */ + +#include "imx8mp.dtsi" + +/ { + model = "DH electronics i.MX8M Plus DHCOM SoM"; + compatible = "dh,imx8mp-dhcom-som", "fsl,imx8mp"; + + aliases { + ethernet0 = &eqos; + ethernet1 = &fec; + rtc0 = &rv3032; + rtc1 = &snvs_rtc; + spi0 = &flexspi; + }; + + memory@40000000 { + device_type = "memory"; + /* Memory size 512 MiB..8 GiB will be filled by U-Boot */ + reg = <0x0 0x40000000 0 0x08000000>; + }; + + reg_eth_vio: regulator-eth-vio { + compatible = "regulator-fixed"; + gpio = <&gpio2 10 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_enet_vio>; + pinctrl-names = "default"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "eth_vio"; + vin-supply = <&buck4>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 19 0>; /* SD2_RESET */ + off-on-delay-us = <12000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_vmmc>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VDD_3V3_SD"; + startup-delay-us = <100>; + vin-supply = <&buck4>; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +&eqos { /* First ethernet */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-handle = <ðphy0g>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + /* Up to one of these two PHYs may be populated. */ + ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */ + compatible = "ethernet-phy-id0007.c110", + "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio3>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_ethphy0>; + pinctrl-names = "default"; + reg = <1>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; + /* Non-default PHY population option. */ + status = "disabled"; + }; + + ethphy0g: ethernet-phy@5 { /* Micrel KSZ9131RNXI */ + compatible = "ethernet-phy-id0022.1642", + "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio3>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <0>; + pinctrl-0 = <&pinctrl_ethphy0>; + pinctrl-names = "default"; + reg = <5>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; + /* Default PHY population option. */ + status = "okay"; + }; + }; +}; + +&fec { /* Second ethernet */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-handle = <ðphy1f>; + phy-mode = "rgmii"; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Up to one PHY may be populated. */ + ethphy1f: ethernet-phy@1 { /* SMSC LAN8740Ai */ + compatible = "ethernet-phy-id0007.c110", + "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio4>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_ethphy1>; + pinctrl-names = "default"; + reg = <1>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + /* Non-default PHY population option. */ + status = "disabled"; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "disabled"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "disabled"; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi>; + status = "okay"; + + flash@0 { /* W25Q128JWPIM */ + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&gpio1 { + gpio-line-names = + "DHCOM-G", "", "", "", "", "DHCOM-I", "DHCOM-J", "DHCOM-L", + "DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "DHCOM-K", "", "", "", "", + "", "", "", "", "DHCOM-INT", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "SOM-HW0", "", + "", "", "", "", "", "", "SOM-MEM0", "SOM-MEM1", + "SOM-MEM2", "SOM-HW2", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "SOM-HW1", "", "", "", "", + "", "", "", "DHCOM-D", "", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "DHCOM-C", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "DHCOM-E", "DHCOM-F", + "", "", "", "", "", "", "", ""; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic: pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + + /* + * i.MX 8M Plus Data Sheet for Consumer Products + * 3.1.4 Operating ranges + * MIMX8ML8CVNKZAB + */ + regulators { + buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */ + regulator-compatible = "BUCK1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-ramp-delay = <3125>; + regulator-always-on; + regulator-boot-on; + }; + + buck2: BUCK2 { /* VDD_ARM */ + regulator-compatible = "BUCK2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-ramp-delay = <3125>; + regulator-always-on; + regulator-boot-on; + }; + + buck4: BUCK4 { /* VDD_3V3 */ + regulator-compatible = "BUCK4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck5: BUCK5 { /* VDD_1V8 */ + regulator-compatible = "BUCK5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6: BUCK6 { /* NVCC_DRAM_1V1 */ + regulator-compatible = "BUCK6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1: LDO1 { /* NVCC_SNVS_1V8 */ + regulator-compatible = "LDO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo3: LDO3 { /* VDDA_1V8 */ + regulator-compatible = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4: LDO4 { /* PMIC_LDO4 */ + regulator-compatible = "LDO4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo5: LDO5 { /* NVCC_SD2 */ + regulator-compatible = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + adc@48 { + compatible = "ti,tla2024"; + reg = <0x48>; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { /* Voltage over AIN0 and AIN1. */ + reg = <0>; + }; + + channel@1 { /* Voltage over AIN0 and AIN3. */ + reg = <1>; + }; + + channel@2 { /* Voltage over AIN1 and AIN3. */ + reg = <2>; + }; + + channel@3 { /* Voltage over AIN2 and AIN3. */ + reg = <3>; + }; + + channel@4 { /* Voltage over AIN0 and GND. */ + reg = <4>; + }; + + channel@5 { /* Voltage over AIN1 and GND. */ + reg = <5>; + }; + + channel@6 { /* Voltage over AIN2 and GND. */ + reg = <6>; + }; + + channel@7 { /* Voltage over AIN3 and GND. */ + reg = <7>; + }; + }; + + touchscreen@49 { + compatible = "ti,tsc2004"; + reg = <0x49>; + interrupts-extended = <&gpio4 0 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + vio-supply = <&buck4>; + }; + + eeprom0: eeprom@50 { /* EEPROM with EQoS MAC address */ + compatible = "atmel,24c02"; + pagesize = <16>; + reg = <0x50>; + }; + + rv3032: rtc@51 { + compatible = "microcrystal,rv3032"; + reg = <0x51>; + interrupts-extended = <&gpio5 5 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + }; + + eeprom1: eeprom@53 { /* EEPROM with FEC MAC address */ + compatible = "atmel,24c02"; + pagesize = <16>; + reg = <0x53>; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c5 { /* HDMI EDID bus */ + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c5>; + pinctrl-1 = <&pinctrl_i2c5_gpio>; + scl-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pinctrl_pwm1>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&uart1 { + /* CA53 console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + /* Bluetooth */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_vbus>; + dr_mode = "otg"; + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +/* SDIO WiFi */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + vmmc-supply = <&buck4>; + bus-width = <4>; + non-removable; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + brcmf: bcrmf@1 { /* muRata 2AE */ + reg = <1>; + compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac"; + /* + * The "host-wake" interrupt output is by default not + * connected to the SoC, but can be connected on to + * SoC pin on the carrier board. + */ + reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + }; +}; + +/* SD slot */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + vmmc-supply = <&buck4>; + vqmmc-supply = <&buck5>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_hog_base + &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c + &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f + &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i + &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l + /* GPIO_M is connected to CLKOUT2 */ + &pinctrl_dhcom_int>; + pinctrl-names = "default"; + + pinctrl_dhcom_a: dhcom-a-grp { + fsl,pins = < + /* ENET_QOS_EVENT0-OUT */ + MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x2 + >; + }; + + pinctrl_dhcom_b: dhcom-b-grp { + fsl,pins = < + /* ENET_QOS_EVENT0-IN */ + MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x2 + >; + }; + + pinctrl_dhcom_c: dhcom-c-grp { + fsl,pins = < + /* GPIO_C */ + MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x2 + >; + }; + + pinctrl_dhcom_d: dhcom-d-grp { + fsl,pins = < + /* GPIO_D */ + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x2 + >; + }; + + pinctrl_dhcom_e: dhcom-e-grp { + fsl,pins = < + /* GPIO_E */ + MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x2 + >; + }; + + pinctrl_dhcom_f: dhcom-f-grp { + fsl,pins = < + /* GPIO_F */ + MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x2 + >; + }; + + pinctrl_dhcom_g: dhcom-g-grp { + fsl,pins = < + /* GPIO_G */ + MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x2 + >; + }; + + pinctrl_dhcom_h: dhcom-h-grp { + fsl,pins = < + /* GPIO_H */ + MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x2 + >; + }; + + pinctrl_dhcom_i: dhcom-i-grp { + fsl,pins = < + /* CSI1_SYNC */ + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x2 + >; + }; + + pinctrl_dhcom_j: dhcom-j-grp { + fsl,pins = < + /* CSIx_#RST */ + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x2 + >; + }; + + pinctrl_dhcom_k: dhcom-k-grp { + fsl,pins = < + /* CSIx_PWDN */ + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x2 + >; + }; + + pinctrl_dhcom_l: dhcom-l-grp { + fsl,pins = < + /* CSI2_SYNC */ + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x2 + >; + }; + + pinctrl_dhcom_int: dhcom-int-grp { + fsl,pins = < + /* INT_HIGHEST_PRIO */ + MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x2 + >; + }; + + pinctrl_hog_base: dhcom-hog-base-grp { + fsl,pins = < + /* GPIOs for memory coding */ + MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x40000080 + MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x40000080 + MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x40000080 + /* GPIOs for hardware coding */ + MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000080 + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x40000080 + MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x40000080 + >; + }; + + pinctrl_ecspi1: dhcom-ecspi1-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x44 + MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x44 + MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x44 + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40 + >; + }; + + pinctrl_ecspi2: dhcom-ecspi2-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x44 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x44 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x44 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40 + >; + }; + + pinctrl_eqos: dhcom-eqos-grp { /* RGMII */ + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + >; + }; + + pinctrl_enet_vio: dhcom-enet-vio-grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x22 + >; + }; + + pinctrl_ethphy0: dhcom-ethphy0-grp { + fsl,pins = < + /* ENET1_#RST Reset */ + MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x22 + /* ENET1_#INT Interrupt */ + MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x22 + >; + }; + + pinctrl_ethphy1: dhcom-ethphy1-grp { + fsl,pins = < + /* ENET1_#RST Reset */ + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x11 + /* ENET1_#INT Interrupt */ + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x11 + >; + }; + + pinctrl_fec: dhcom-fec-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x1f + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f + MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x1f + >; + }; + + pinctrl_flexcan1: dhcom-flexcan1-grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 + >; + }; + + pinctrl_flexcan2: dhcom-flexcan2-grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x154 + MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x154 + >; + }; + + pinctrl_flexspi: dhcom-flexspi-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + >; + }; + + pinctrl_hdmi: dhcom-hdmi-grp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x154 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x154 + >; + }; + + pinctrl_i2c3: dhcom-i2c3-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x40000084 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x40000084 + >; + }; + + pinctrl_i2c3_gpio: dhcom-i2c3-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x84 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x84 + >; + }; + + pinctrl_i2c4: dhcom-i2c4-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x40000084 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x40000084 + >; + }; + + pinctrl_i2c4_gpio: dhcom-i2c4-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x84 + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x84 + >; + }; + + pinctrl_i2c5: dhcom-i2c5-grp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x40000084 + MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x40000084 + >; + }; + + pinctrl_i2c5_gpio: dhcom-i2c5-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x84 + MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x84 + >; + }; + + pinctrl_pmic: dhcom-pmic-grp { + fsl,pins = < + /* PMIC_nINT */ + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090 + >; + }; + + pinctrl_pwm1: dhcom-pwm1-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x6 + >; + }; + + pinctrl_rtc: dhcom-rtc-grp { + fsl,pins = < + /* RTC_#INT Interrupt */ + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x40000080 + >; + }; + + pinctrl_touch: dhcom-touch-grp { + fsl,pins = < + /* #TOUCH_INT */ + MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x40000080 + >; + }; + + pinctrl_uart1: dhcom-uart1-grp { + fsl,pins = < + /* Console UART */ + MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x49 + MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x49 + MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x49 + MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x49 + >; + }; + + pinctrl_uart2: dhcom-uart2-grp { + fsl,pins = < + /* Bluetooth UART */ + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 + MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x49 + MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x49 + >; + }; + + pinctrl_uart3: dhcom-uart3-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x49 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x49 + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x49 + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x49 + >; + }; + + pinctrl_uart4: dhcom-uart4-grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 + >; + }; + + pinctrl_usb0_vbus: dhcom-usb0-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x0 + >; + }; + + pinctrl_usb1_vbus: dhcom-usb1-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x6 + MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x80 + >; + }; + + pinctrl_usdhc1: dhcom-usdhc1-grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + /* BT_REG_EN */ + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144 + /* WL_REG_EN */ + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 + >; + }; + + pinctrl_usdhc1_100mhz: dhcom-usdhc1-100mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + /* BT_REG_EN */ + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144 + /* WL_REG_EN */ + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 + >; + }; + + pinctrl_usdhc1_200mhz: dhcom-usdhc1-200mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + /* BT_REG_EN */ + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144 + /* WL_REG_EN */ + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 + >; + }; + + pinctrl_usdhc2: dhcom-usdhc2-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: dhcom-usdhc2-100mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: dhcom-usdhc2-200mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_vmmc: dhcom-usdhc2-vmmc-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x20 + >; + }; + + pinctrl_usdhc2_gpio: dhcom-usdhc2-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40000080 + >; + }; + + pinctrl_usdhc3: dhcom-usdhc3-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 + >; + }; + + pinctrl_usdhc3_100mhz: dhcom-usdhc3-100mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 + >; + }; + + pinctrl_usdhc3_200mhz: dhcom-usdhc3-200mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 + >; + }; + + pinctrl_wdog: dhcom-wdog-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 9a4de739e6a2..f6b017ab5f53 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -67,18 +67,20 @@ }; }; -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can1_stby>; - status = "okay"; +&A53_0 { + cpu-supply = <®_arm>; }; -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can2_stby>; - status = "disabled";/* can2 pin conflict with pdm */ +&A53_1 { + cpu-supply = <®_arm>; +}; + +&A53_2 { + cpu-supply = <®_arm>; +}; + +&A53_3 { + cpu-supply = <®_arm>; }; &eqos { @@ -197,6 +199,20 @@ }; }; +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_stby>; + status = "disabled";/* can2 pin conflict with pdm */ +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -221,7 +237,7 @@ regulator-ramp-delay = <3125>; }; - BUCK2 { + reg_arm: BUCK2 { regulator-name = "BUCK2"; regulator-min-microvolt = <720000>; regulator-max-microvolt = <1025000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts new file mode 100644 index 000000000000..d8ca52976170 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -0,0 +1,702 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2021-2022 TQ-Systems GmbH + * Author: Alexander Stein <alexander.stein@tq-group.com> + */ + +/dts-v1/; + +#include <dt-bindings/leds/common.h> +#include <dt-bindings/net/ti-dp83867.h> +#include <dt-bindings/pwm/pwm.h> +#include "imx8mp-tqma8mpql.dtsi" + +/ { + model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL"; + compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp"; + + chosen { + stdout-path = &uart4; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>; + }; + + aliases { + mmc0 = &usdhc3; + mmc1 = &usdhc2; + mmc2 = &usdhc1; + rtc0 = &pcf85063; + rtc1 = &snvs_rtc; + spi0 = &flexspi; + spi1 = &ecspi1; + spi2 = &ecspi2; + spi3 = &ecspi3; + }; + + backlight_lvds: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + pwms = <&pwm2 0 5000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_vcc_12v0>; + enable-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiobutton>; + autorepeat; + + switch-1 { + label = "S12"; + linux,code = <BTN_0>; + gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; + }; + + switch-2 { + label = "S13"; + linux,code = <BTN_1>; + gpios = <&gpio5 27 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpioled>; + + led-0 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + function-enumerator = <0>; + gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-1 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-2 { + color = <LED_COLOR_ID_YELLOW>; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + }; + }; + + display: display { + /* + * Display is not fixed, so compatible has to be added from + * DT overlay + */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvdsdisplay>; + power-supply = <®_vcc_3v3>; + enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; + backlight = <&backlight_lvds>; + status = "disabled"; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + reg_vcc_12v0: regulator-12v0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg12v0>; + regulator-name = "VCC_12V0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vcc_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ocram: ocram@900000 { + no-map; + reg = <0 0x900000 0 0x70000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x38000000>; + alloc-ranges = <0 0x40000000 0 0xB0000000>; + linux,cma-default; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; + status = "okay"; + + adc: adc@0 { + reg = <0>; + compatible = "microchip,mcp3202"; + /* 100 ksps * 18 */ + spi-max-frequency = <1800000>; + vref-supply = <®_vcc_3v3>; + #io-channel-cells = <1>; + }; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>, <&pinctrl_eqos_phy>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy3>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy3: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + enet-phy-lane-no-swap; + interrupt-parent = <&gpio4>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>, <&pinctrl_fec_phy>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + enet-phy-lane-no-swap; + interrupt-parent = <&gpio4>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_vcc_3v3>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_vcc_3v3>; + status = "okay"; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>; + + gpio-line-names = "GPO1", "GPO0", "", "GPO3", + "", "", "GPO2", "GPI0", + "PMIC_IRQ", "GPI1", "OTG_ID", "USB_HUB_RST#", + "OTG_PWR", "", "GPI2", "GPI3", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hoggpio2>; + + gpio-line-names = "", "", "", "", + "", "", "VCC12V_EN", "PERST#", + "", "", "CLKREQ#", "PEWAKE#", + "USDHC2_CD", "", "", "", + "", "", "", "V_SD3V3_EN", + "", "", "", "", + "", "", "", "", + "", "", "", ""; + + perst-hog { + gpio-hog; + gpios = <7 0>; + output-high; + line-name = "PERST#"; + }; + + clkreq-hog { + gpio-hog; + gpios = <10 0>; + input; + line-name = "CLKREQ#"; + }; + + pewake-hog { + gpio-hog; + gpios = <11 0>; + input; + line-name = "PEWAKE#"; + }; +}; + +&gpio3 { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "LVDS0_RESET#", "", + "", "", "", "LVDS0_BLT_EN", + "LVDS0_PWR_EN", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio4>; + + gpio-line-names = "ENET0_RST#", "ENET0_INT#", "ENET1_RST#", "ENET1_INT#", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "DP_IRQ", "DSI_EN", + "HDMI_OC#", "TEMP_EVENT#", "PCIE_CLK_OE#", "", + "", "", "", "FAN_PWR", + "RTC_EVENT#", "CODEC_RST#", "", ""; +}; + +&gpio5 { + gpio-line-names = "", "", "", "LED2", + "LED1", "LED0", "CSI0_RESET#", "CSI0_SYNC", + "CSI0_TRIGGER", "CSI0_ENABLE", "", "", + "", "ECSPI2_SS0", "", "", + "", "", "", "", + "", "", "", "", + "", "ECSPI3_SS0", "SWITCH_A", "SWITCH_B", + "", "", "", ""; +}; + +&i2c2 { + clock-frequency = <384000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + /* NXP SE97BTP with temperature sensor + eeprom */ + se97_1c: temperature-sensor-eeprom@1c { + compatible = "nxp,se97", "jedec,jc-42.4-temp"; + reg = <0x1c>; + }; + + at24c02_54: eeprom@54 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x54>; + pagesize = <16>; + vcc-supply = <®_vcc_3v3>; + }; +}; + +&i2c4 { + clock-frequency = <384000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c6 { + clock-frequency = <384000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c6>; + pinctrl-1 = <&pinctrl_i2c6_gpio>; + scl-gpios = <&gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&pcf85063 { + /* RTC_EVENT# is connected on MBa8MPxL */ + interrupt-parent = <&gpio4>; + interrupts = <28 IRQ_TYPE_EDGE_FALLING>; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MP_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + assigned-clocks = <&clk IMX8MP_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + status = "okay"; +}; + +&uart4 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + no-mmc; + no-sdio; + disable-wp; + bus-width = <4>; + status = "okay"; +}; + +&iomuxc { + pinctrl_backlight: backlightgrp { + fsl,pins = <MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x14>; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = <MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x150>, + <MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x150>; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = <MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x150>, + <MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x150>; + }; + + /* only on X57, primary used as CSI0 control signals */ + pinctrl_ecspi1: ecspi1grp { + fsl,pins = <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c0>, + <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x1c0>, + <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x1c0>, + <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c0>; + }; + + /* on X63 and optionally on X57, can also be used as CSI1 control signals */ + pinctrl_ecspi2: ecspi2grp { + fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x1c0>, + <MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x1c0>, + <MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x1c0>, + <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c0>; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = <MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x1c0>, + <MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x1c0>, + <MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x1c0>, + <MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x1c0>; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x40000044>, + <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x40000044>, + <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90>, + <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90>, + <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90>, + <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90>, + <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90>, + <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90>, + <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12>, + <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12>, + <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12>, + <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12>, + <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12>, + <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x14>; + }; + + pinctrl_eqos_event: eqosevtgrp { + fsl,pins = <MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT 0x100>, + <MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN 0x1c0>; + }; + + pinctrl_eqos_phy: eqosphygrp { + fsl,pins = <MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x100>, + <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x1c0>; + }; + + pinctrl_fec: fecgrp { + fsl,pins = <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x40000044>, + <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x40000044>, + <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90>, + <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90>, + <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90>, + <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90>, + <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90>, + <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90>, + <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12>, + <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12>, + <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x12>, + <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x12>, + <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x12>, + <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14>; + }; + + pinctrl_fec_event: fecevtgrp { + fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x100>, + <MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x1c0>; + }; + + pinctrl_fec_phy: fecphygrp { + fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x100>, + <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x1c0>; + }; + + pinctrl_fec_phyalt: fecphyaltgrp { + fsl,pins = <MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x180>, + <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x180>; + }; + + pinctrl_gpiobutton: gpiobuttongrp { + fsl,pins = <MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x10>, + <MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x10>; + }; + + pinctrl_gpioled: gpioledgrp { + fsl,pins = <MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x14>, + <MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x14>, + <MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x14>; + }; + + pinctrl_gpio1: gpio1grp { + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x10>, + <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x10>, + <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x10>, + <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x10>, + <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x80>, + <MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x80>, + <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x80>, + <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x80>; + }; + + pinctrl_gpio4: gpio4grp { + fsl,pins = <MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x180>, + <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x180>; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2>, + <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2>, + <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010>, + <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000010>; + }; + + pinctrl_hoggpio2: hoggpio2grp { + fsl,pins = <MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x140>, + <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x140>, + <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140>; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001e2>, + <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001e2>; + }; + + pinctrl_i2c2_gpio: i2c2-gpiogrp { + fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001e2>, + <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001e2>; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001e2>, + <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001e2>; + }; + + pinctrl_i2c4_gpio: i2c4-gpiogrp { + fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001e2>, + <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001e2>; + }; + + pinctrl_i2c6: i2c6grp { + fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x400001e2>, + <MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x400001e2>; + }; + + pinctrl_i2c6_gpio: i2c6-gpiogrp { + fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x400001e2>, + <MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x400001e2>; + }; + + pinctrl_lvdsdisplay: lvdsdisplaygrp { + fsl,pins = <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x10>; /* Power enable */ + }; + + /* LVDS Backlight */ + pinctrl_pwm2: pwm2grp { + fsl,pins = <MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x14>; + }; + + /* FAN */ + pinctrl_pwm3: pwm3grp { + fsl,pins = <MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT 0x14>; + }; + + pinctrl_reg12v0: reg12v0grp { + fsl,pins = <MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x140>; /* VCC12V enable */ + }; + + /* X61 */ + pinctrl_uart1: uart1grp { + fsl,pins = <MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x140>, + <MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x140>; + }; + + /* X61 */ + pinctrl_uart2: uart2grp { + fsl,pins = <MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x140>, + <MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x140>; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = <MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x140>, + <MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x140>; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140>, + <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140>; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x192>, + <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d2>, + <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>, + <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>, + <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>, + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>, + <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, + <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, + <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, + <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, + <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, + <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, + <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, + <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, + <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, + <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, + <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c0>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi new file mode 100644 index 000000000000..7bd680a926ce --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi @@ -0,0 +1,284 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2021-2022 TQ-Systems GmbH + * Author: Alexander Stein <alexander.stein@tq-group.com> + */ + +#include "imx8mp.dtsi" + +/ { + model = "TQ-Systems i.MX8MPlus TQMa8MPxL"; + compatible = "tq,imx8mp-tqma8mpql", "fsl,imx8mp"; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + /* identical to buck4_reg, but should never change */ + reg_vcc3v3: regulator-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* e-MMC IO, needed for HS modes */ + reg_vcc1v8: regulator-vcc1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + }; +}; + +&i2c1 { + clock-frequency = <384000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + /* NXP SE97BTP with temperature sensor + eeprom */ + se97: temperature-sensor-eeprom@1b { + compatible = "nxp,se97", "jedec,jc-42.4-temp"; + reg = <0x1b>; + }; + + pmic: pmic@25 { + reg = <0x25>; + compatible = "nxp,pca9450c"; + + /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */ + pinctrl-0 = <&pinctrl_pmic>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + + regulators { + /* V_0V85_SOC: 0.85 .. 0.95 */ + buck1_reg: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + /* VDD_ARM */ + buck2_reg: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + regulator-ramp-delay = <3125>; + }; + + /* VCC3V3 -> VMMC, ... must not be changed */ + buck4_reg: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */ + buck5_reg: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V1 -> RAM, ... must not be changed */ + buck6_reg: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8_SNVS */ + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8_ANA */ + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* unused */ + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + /* VCC SD IO - switched using SD2 VSELECT */ + ldo5_reg: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + pcf85063: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + }; + + at24c02: eeprom@53 { + compatible = "nxp,se97b", "atmel,24c02"; + read-only; + reg = <0x53>; + pagesize = <16>; + vcc-supply = <®_vcc3v3>; + }; + + m24c64: eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + vcc-supply = <®_vcc3v3>; + }; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc1v8>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_flexspi0: flexspi0grp { + fsl,pins = <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x142>, + <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82>, + <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82>, + <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82>, + <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82>, + <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82>; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001e2>, + <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001e2>; + }; + + pinctrl_i2c1_gpio: i2c1-gpiogrp { + fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001e2>, + <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001e2>; + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x1c0>; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x10>; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, + <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>, + <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>, + <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>, + <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>, + <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>, + <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>, + <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>, + <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>, + <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>, + <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x84>, + <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x84>; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, + <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>, + <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>, + <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>, + <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>, + <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>, + <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>, + <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>, + <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>, + <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>, + <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x84>, + <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x84>; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, + <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>, + <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>, + <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>, + <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>, + <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>, + <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>, + <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>, + <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>, + <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>, + <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x84>, + <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x84>; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x1c4>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi index fb17e329cd37..c5987bdbb383 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -49,7 +49,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - wakeup { + button-wakeup { debounce-interval = <10>; /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; @@ -146,6 +146,14 @@ }; }; +&cpu_alert0 { + temperature = <95000>; +}; + +&cpu_crit0 { + temperature = <105000>; +}; + /* Verdin SPI_1 */ &ecspi1 { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 410d0d5e6f1e..fe178b7d063c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -195,7 +195,7 @@ clk_ext4: clock-ext4 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency= <133000000>; + clock-frequency = <133000000>; clock-output-names = "clk_ext4"; }; @@ -293,7 +293,7 @@ arm,no-tick-in-suspend; }; - soc@0 { + soc: soc@0 { compatible = "fsl,imx8mp-soc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -791,6 +791,7 @@ compatible = "fsl,sec-v4.0-job-ring"; reg = <0x1000 0x1000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; }; sec_jr1: jr@2000 { @@ -903,7 +904,7 @@ <&clk IMX8MP_CLK_USDHC1_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; @@ -917,7 +918,7 @@ <&clk IMX8MP_CLK_USDHC2_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; @@ -931,7 +932,7 @@ <&clk IMX8MP_CLK_USDHC3_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; @@ -1018,6 +1019,26 @@ }; }; + noc: interconnect@32700000 { + compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc"; + reg = <0x32700000 0x100000>; + clocks = <&clk IMX8MP_CLK_NOC>; + #interconnect-cells = <1>; + operating-points-v2 = <&noc_opp_table>; + + noc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200M { + opp-hz = /bits/ 64 <200000000>; + }; + + opp-1000M { + opp-hz = /bits/ 64 <1000000000>; + }; + }; + }; + aips4: bus@32c00000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x32c00000 0x400000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 99fed35168eb..82387b9cb800 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -71,12 +71,36 @@ linux,autosuspend-period = <125>; }; + audio_codec_bt_sco: audio-codec-bt-sco { + compatible = "linux,bt-sco"; + #sound-dai-cells = <1>; + }; + wm8524: audio-codec { #sound-dai-cells = <0>; compatible = "wlf,wm8524"; wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; }; + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai3>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&audio_codec_bt_sco 1>; + }; + }; + sound-wm8524 { compatible = "simple-audio-card"; simple-audio-card,name = "wm8524-audio"; @@ -386,6 +410,16 @@ status = "okay"; }; +&sai3 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -548,6 +582,15 @@ >; }; + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 + >; + }; + pinctrl_spdif1: spdif1grp { fsl,pins = < MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts index b86f188a440d..6445c6b90b5b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts @@ -36,21 +36,21 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - btn1 { + button-1 { label = "VOL_UP"; gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; wakeup-source; linux,code = <KEY_VOLUMEUP>; }; - btn2 { + button-2 { label = "VOL_DOWN"; gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; wakeup-source; linux,code = <KEY_VOLUMEDOWN>; }; - wwan-wake { + button-3 { label = "WWAN_WAKE"; gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio3>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 587e55aaa57b..9eec8a7eecfc 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -37,7 +37,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_keys>; - vol-down { + key-vol-down { label = "VOL_DOWN"; gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; @@ -45,7 +45,7 @@ wakeup-source; }; - vol-up { + key-vol-up { label = "VOL_UP"; gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts index f70fb32b96b0..9dda2a1554c3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts @@ -26,7 +26,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - power { + button-power { label = "Power Button"; gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; @@ -152,7 +152,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_arm_dram>; reg = <0x60>; - regulator-min-microvolt = <900000>; + regulator-min-microvolt = <900000>; regulator-max-microvolt = <1000000>; regulator-always-on; vsel-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; @@ -186,7 +186,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_soc_gpu_vpu>; reg = <0x60>; - regulator-min-microvolt = <900000>; + regulator-min-microvolt = <900000>; regulator-max-microvolt = <1000000>; regulator-always-on; vsel-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi index 2222ef7b3eab..4e05120c62d4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi @@ -443,7 +443,7 @@ status = "okay"; usbhub: usbhub@2c { - compatible ="microchip,usb2513b"; + compatible = "microchip,usb2513b"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbhub>; reg = <0x2c>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 49eadb081b19..e9f0cdd10ab6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -94,7 +94,7 @@ clk_ext4: clock-ext4 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency= <133000000>; + clock-frequency = <133000000>; clock-output-names = "clk_ext4"; }; @@ -320,7 +320,7 @@ arm,no-tick-in-suspend; }; - soc@0 { + soc: soc@0 { compatible = "fsl,imx8mq-soc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -329,7 +329,7 @@ nvmem-cells = <&imx8mq_uid>; nvmem-cell-names = "soc_unique_id"; - bus@30000000 { /* AIPS1 */ + aips1: bus@30000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30000000 0x400000>; #address-cells = <1>; @@ -507,7 +507,7 @@ <0x00030005 0x00000053>, <0x00030006 0x0000005f>, <0x00030007 0x00000071>; - #thermal-sensor-cells = <1>; + #thermal-sensor-cells = <1>; }; wdog1: watchdog@30280000 { @@ -784,7 +784,7 @@ }; }; - bus@30400000 { /* AIPS2 */ + aips2: bus@30400000 { /* AIPS2 */ compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30400000 0x400000>; #address-cells = <1>; @@ -844,7 +844,7 @@ }; }; - bus@30800000 { /* AIPS3 */ + aips3: bus@30800000 { /* AIPS3 */ compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30800000 0x400000>; #address-cells = <1>; @@ -1018,6 +1018,7 @@ compatible = "fsl,sec-v4.0-job-ring"; reg = <0x1000 0x1000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; }; sec_jr1: jr@2000 { @@ -1369,7 +1370,7 @@ }; }; - bus@32c00000 { /* AIPS4 */ + aips4: bus@32c00000 { /* AIPS4 */ compatible = "fsl,aips-bus", "simple-bus"; reg = <0x32c00000 0x400000>; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index 4f767012f1f5..c9c2b6536233 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -181,7 +181,7 @@ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ }; - scu { + system-controller { compatible = "fsl,imx-scu"; mbox-names = "tx0", "rx0", @@ -190,7 +190,7 @@ &lsio_mu1 1 0 &lsio_mu1 3 3>; - pd: imx8qx-pd { + pd: power-controller { compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd"; #power-domain-cells = <1>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi index 144fc9e82da7..a08e70fb7c7a 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi @@ -16,7 +16,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpiokeys>; - wakeup { + key-wakeup { label = "Wake-Up"; gpios = <&lsio_gpio3 10 GPIO_ACTIVE_HIGH>; linux,code = <KEY_WAKEUP>; @@ -38,17 +38,17 @@ /* Colibri UART_B */ &lpuart0 { - status= "okay"; + status = "okay"; }; /* Colibri UART_C */ &lpuart2 { - status= "okay"; + status = "okay"; }; /* Colibri UART_A */ &lpuart3 { - status= "okay"; + status = "okay"; }; /* Colibri FastEthernet */ diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index a79ae33cbad2..f4ea18bb95ab 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -201,7 +201,7 @@ method = "smc"; }; - scu { + system-controller { compatible = "fsl,imx-scu"; mbox-names = "tx0", "rx0", @@ -210,29 +210,27 @@ &lsio_mu1 1 0 &lsio_mu1 3 3>; - pd: imx8qx-pd { + pd: power-controller { compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; #power-domain-cells = <1>; }; clk: clock-controller { - compatible = "fsl,imx8qxp-clk"; + compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; #clock-cells = <2>; - clocks = <&xtal32k &xtal24m>; - clock-names = "xtal_32KHz", "xtal_24Mhz"; }; iomuxc: pinctrl { compatible = "fsl,imx8qxp-iomuxc"; }; - ocotp: imx8qx-ocotp { + ocotp: ocotp { compatible = "fsl,imx8qxp-scu-ocotp"; #address-cells = <1>; #size-cells = <1>; }; - scu_key: scu-key { + scu_key: keys { compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; linux,keycodes = <KEY_POWER>; status = "disabled"; @@ -276,7 +274,7 @@ }; thermal_zones: thermal-zones { - cpu-thermal0 { + cpu0-thermal { polling-delay-passive = <250>; polling-delay = <2000>; thermal-sensors = <&tsens IMX_SC_R_SYSTEM>; diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index 09f7364dd1d0..60c1b018bf03 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -137,7 +137,7 @@ }; }; - soc@0 { + soc: soc@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -331,7 +331,7 @@ clock-names = "ipg", "ahb", "per"; power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; @@ -346,7 +346,7 @@ clock-names = "ipg", "ahb", "per"; power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; @@ -361,13 +361,13 @@ clock-names = "ipg", "ahb", "per"; power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; }; - gpioe: gpio@2d000000 { + gpioe: gpio@2d000080 { compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; reg = <0x2d000080 0x1000>, <0x2d000040 0x40>; gpio-controller; @@ -381,7 +381,7 @@ gpio-ranges = <&iomuxc1 0 32 24>; }; - gpiof: gpio@2d010000 { + gpiof: gpio@2d010080 { compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; reg = <0x2d010080 0x1000>, <0x2d010040 0x40>; gpio-controller; @@ -417,7 +417,7 @@ }; }; - gpiod: gpio@2e200000 { + gpiod: gpio@2e200080 { compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; reg = <0x2e200080 0x1000>, <0x2e200040 0x40>; gpio-controller; diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts new file mode 100644 index 000000000000..69786c326db0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +/dts-v1/; + +#include "imx93.dtsi" + +/ { + model = "NXP i.MX93 11X11 EVK board"; + compatible = "fsl,imx93-11x11-evk", "fsl,imx93"; + + chosen { + stdout-path = &lpuart1; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&mu1 { + status = "okay"; +}; + +&mu2 { + status = "okay"; +}; + +&lpuart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; + no-sdio; + no-mmc; +}; + +&iomuxc { + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x17fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x17fe + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x17fe + MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx93-pinfunc.h b/arch/arm64/boot/dts/freescale/imx93-pinfunc.h new file mode 100755 index 000000000000..4298a145f8a9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-pinfunc.h @@ -0,0 +1,623 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright 2022 NXP + */ + +#ifndef __DTS_IMX93_PINFUNC_H +#define __DTS_IMX93_PINFUNC_H + +/* + * The pin function ID is a tuple of + * <mux_reg conf_reg input_reg mux_mode input_val> + */ +#define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0 +#define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0 +#define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0 +#define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0 +#define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0 +#define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x01B8 0x03D4 0x0 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x0008 0x01B8 0x0000 0x4 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x0008 0x01B8 0x0000 0x5 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x01B8 0x042C 0x6 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000C 0x01BC 0x0000 0x0 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x000C 0x01BC 0x0000 0x1 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000C 0x01BC 0x0364 0x3 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x000C 0x01BC 0x0000 0x4 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x000C 0x01BC 0x0000 0x5 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000C 0x01BC 0x0434 0x6 0x0 +#define MX93_PAD_GPIO_IO00__GPIO2_IO00 0x0010 0x01C0 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x01C0 0x03E4 0x11 0x0 +#define MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x0010 0x01C0 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x0010 0x01C0 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x01C0 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x01C0 0x0434 0x5 0x1 +#define MX93_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x01C0 0x03EC 0x16 0x0 +#define MX93_PAD_GPIO_IO00__FLEXIO1_FLEXIO00 0x0010 0x01C0 0x036C 0x7 0x0 +#define MX93_PAD_GPIO_IO01__GPIO2_IO01 0x0014 0x01C4 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x01C4 0x03E0 0x11 0x0 +#define MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00 0x0014 0x01C4 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x0014 0x01C4 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x01C4 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x01C4 0x0430 0x5 0x1 +#define MX93_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x01C4 0x03E8 0x16 0x0 +#define MX93_PAD_GPIO_IO01__FLEXIO1_FLEXIO01 0x0014 0x01C4 0x0370 0x7 0x0 +#define MX93_PAD_GPIO_IO02__GPIO2_IO02 0x0018 0x01C8 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x01C8 0x0000 0x11 0x0 +#define MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0x0018 0x01C8 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x0018 0x01C8 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x01C8 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x01C8 0x042C 0x5 0x1 +#define MX93_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x01C8 0x03F4 0x16 0x0 +#define MX93_PAD_GPIO_IO02__FLEXIO1_FLEXIO02 0x0018 0x01C8 0x0374 0x7 0x0 +#define MX93_PAD_GPIO_IO03__GPIO2_IO03 0x001C 0x01CC 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO03__LPI2C4_SCL 0x001C 0x01CC 0x0000 0x11 0x0 +#define MX93_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0x001C 0x01CC 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x001C 0x01CC 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x001C 0x01CC 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO03__LPUART5_RTS_B 0x001C 0x01CC 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO03__LPI2C6_SCL 0x001C 0x01CC 0x03F0 0x16 0x0 +#define MX93_PAD_GPIO_IO03__FLEXIO1_FLEXIO03 0x001C 0x01CC 0x0378 0x7 0x0 +#define MX93_PAD_GPIO_IO04__GPIO2_IO04 0x0020 0x01D0 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x01D0 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO04__PDM_CLK 0x0020 0x01D0 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x0020 0x01D0 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x01D0 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x01D0 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x01D0 0x03F4 0x16 0x1 +#define MX93_PAD_GPIO_IO04__FLEXIO1_FLEXIO04 0x0020 0x01D0 0x037C 0x7 0x0 +#define MX93_PAD_GPIO_IO05__GPIO2_IO05 0x0024 0x01D4 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x01D4 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00 0x0024 0x01D4 0x0438 0x2 0x0 +#define MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x0024 0x01D4 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x01D4 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x01D4 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x01D4 0x03F0 0x16 0x1 +#define MX93_PAD_GPIO_IO05__FLEXIO1_FLEXIO05 0x0024 0x01D4 0x0380 0x7 0x0 +#define MX93_PAD_GPIO_IO06__GPIO2_IO06 0x0028 0x01D8 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x01D8 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01 0x0028 0x01D8 0x043C 0x2 0x0 +#define MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x0028 0x01D8 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x01D8 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x01D8 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x01D8 0x03FC 0x16 0x0 +#define MX93_PAD_GPIO_IO06__FLEXIO1_FLEXIO06 0x0028 0x01D8 0x0384 0x7 0x0 +#define MX93_PAD_GPIO_IO07__GPIO2_IO07 0x002C 0x01DC 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO07__LPSPI3_PCS1 0x002C 0x01DC 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA01 0x002C 0x01DC 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x002C 0x01DC 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO07__LPSPI7_SCK 0x002C 0x01DC 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO07__LPUART6_RTS_B 0x002C 0x01DC 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO07__LPI2C7_SCL 0x002C 0x01DC 0x03F8 0x16 0x0 +#define MX93_PAD_GPIO_IO07__FLEXIO1_FLEXIO07 0x002C 0x01DC 0x0388 0x7 0x0 +#define MX93_PAD_GPIO_IO08__GPIO2_IO08 0x0030 0x01E0 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x01E0 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA02 0x0030 0x01E0 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x0030 0x01E0 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x01E0 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x01E0 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x01E0 0x03FC 0x16 0x1 +#define MX93_PAD_GPIO_IO08__FLEXIO1_FLEXIO08 0x0030 0x01E0 0x038C 0x7 0x0 +#define MX93_PAD_GPIO_IO09__GPIO2_IO09 0x0034 0x01E4 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x01E4 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA03 0x0034 0x01E4 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x0034 0x01E4 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x01E4 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x01E4 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x01E4 0x03F8 0x16 0x1 +#define MX93_PAD_GPIO_IO09__FLEXIO1_FLEXIO09 0x0034 0x01E4 0x0390 0x7 0x0 +#define MX93_PAD_GPIO_IO10__GPIO2_IO10 0x0038 0x01E8 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x01E8 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA04 0x0038 0x01E8 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x0038 0x01E8 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x01E8 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x01E8 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x01E8 0x0404 0x16 0x0 +#define MX93_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x0038 0x01E8 0x0394 0x7 0x0 +#define MX93_PAD_GPIO_IO11__GPIO2_IO11 0x003C 0x01EC 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x003C 0x01EC 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA05 0x003C 0x01EC 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x003C 0x01EC 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO11__TPM5_EXTCLK 0x003C 0x01EC 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO11__LPUART7_RTS_B 0x003C 0x01EC 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO11__LPI2C8_SCL 0x003C 0x01EC 0x0400 0x16 0x0 +#define MX93_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x003C 0x01EC 0x0398 0x7 0x0 +#define MX93_PAD_GPIO_IO12__GPIO2_IO12 0x0040 0x01F0 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x01F0 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02 0x0040 0x01F0 0x0440 0x2 0x0 +#define MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x0040 0x01F0 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x01F0 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x01F0 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x01F0 0x0404 0x16 0x1 +#define MX93_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x01F0 0x0450 0x7 0x0 +#define MX93_PAD_GPIO_IO13__GPIO2_IO13 0x0044 0x01F4 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x01F4 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03 0x0044 0x01F4 0x0444 0x2 0x0 +#define MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x0044 0x01F4 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x01F4 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x01F4 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x01F4 0x0400 0x16 0x1 +#define MX93_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x0044 0x01F4 0x039C 0x7 0x0 +#define MX93_PAD_GPIO_IO14__GPIO2_IO14 0x0048 0x01F8 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x01F8 0x041C 0x1 0x0 +#define MX93_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06 0x0048 0x01F8 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x0048 0x01F8 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x01F8 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x01F8 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x01F8 0x0428 0x6 0x0 +#define MX93_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x0048 0x01F8 0x03A0 0x7 0x0 +#define MX93_PAD_GPIO_IO15__GPIO2_IO15 0x004C 0x01FC 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO15__LPUART3_RX 0x004C 0x01FC 0x0418 0x1 0x0 +#define MX93_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07 0x004C 0x01FC 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x004C 0x01FC 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO15__LPSPI8_SCK 0x004C 0x01FC 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO15__LPUART8_RTS_B 0x004C 0x01FC 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO15__LPUART4_RX 0x004C 0x01FC 0x0424 0x6 0x0 +#define MX93_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x004C 0x01FC 0x03A4 0x7 0x0 +#define MX93_PAD_GPIO_IO16__GPIO2_IO16 0x0050 0x0200 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x0050 0x0200 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO16__PDM_BIT_STREAM02 0x0050 0x0200 0x0440 0x2 0x1 +#define MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x0050 0x0200 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0200 0x0414 0x4 0x0 +#define MX93_PAD_GPIO_IO16__LPSPI4_PCS2 0x0050 0x0200 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0200 0x0420 0x6 0x0 +#define MX93_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 0x0050 0x0200 0x03A8 0x7 0x0 +#define MX93_PAD_GPIO_IO17__GPIO2_IO17 0x0054 0x0204 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO17__SAI3_MCLK 0x0054 0x0204 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA08 0x0054 0x0204 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x0054 0x0204 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO17__LPUART3_RTS_B 0x0054 0x0204 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO17__LPSPI4_PCS1 0x0054 0x0204 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO17__LPUART4_RTS_B 0x0054 0x0204 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 0x0054 0x0204 0x03AC 0x7 0x0 +#define MX93_PAD_GPIO_IO18__GPIO2_IO18 0x0058 0x0208 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x0208 0x044C 0x1 0x0 +#define MX93_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09 0x0058 0x0208 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x0058 0x0208 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO18__LPSPI5_PCS0 0x0058 0x0208 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO18__LPSPI4_PCS0 0x0058 0x0208 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO18__TPM5_CH2 0x0058 0x0208 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 0x0058 0x0208 0x03B0 0x7 0x0 +#define MX93_PAD_GPIO_IO19__GPIO2_IO19 0x005C 0x020C 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005C 0x020C 0x0450 0x1 0x1 +#define MX93_PAD_GPIO_IO19__PDM_BIT_STREAM03 0x005C 0x020C 0x0444 0x2 0x1 +#define MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x005C 0x020C 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO19__LPSPI5_SIN 0x005C 0x020C 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO19__LPSPI4_SIN 0x005C 0x020C 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO19__TPM6_CH2 0x005C 0x020C 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x005C 0x020C 0x0000 0x7 0x0 +#define MX93_PAD_GPIO_IO20__GPIO2_IO20 0x0060 0x0210 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x0060 0x0210 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO20__PDM_BIT_STREAM00 0x0060 0x0210 0x0438 0x2 0x1 +#define MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x0060 0x0210 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO20__LPSPI5_SOUT 0x0060 0x0210 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO20__LPSPI4_SOUT 0x0060 0x0210 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO20__TPM3_CH1 0x0060 0x0210 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 0x0060 0x0210 0x03B4 0x7 0x0 +#define MX93_PAD_GPIO_IO21__GPIO2_IO21 0x0064 0x0214 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 0x0064 0x0214 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO21__PDM_CLK 0x0064 0x0214 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x0064 0x0214 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO21__LPSPI5_SCK 0x0064 0x0214 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO21__LPSPI4_SCK 0x0064 0x0214 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO21__TPM4_CH1 0x0064 0x0214 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0214 0x044C 0x7 0x1 +#define MX93_PAD_GPIO_IO22__GPIO2_IO22 0x0068 0x0218 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x0218 0x0458 0x1 0x0 +#define MX93_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x0218 0x0454 0x2 0x0 +#define MX93_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x0068 0x0218 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO22__TPM5_CH1 0x0068 0x0218 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO22__TPM6_EXTCLK 0x0068 0x0218 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x0218 0x03EC 0x16 0x1 +#define MX93_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 0x0068 0x0218 0x03B8 0x7 0x0 +#define MX93_PAD_GPIO_IO23__GPIO2_IO23 0x006C 0x021C 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO23__USDHC3_CMD 0x006C 0x021C 0x045C 0x1 0x0 +#define MX93_PAD_GPIO_IO23__SPDIF_OUT 0x006C 0x021C 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x006C 0x021C 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO23__TPM6_CH1 0x006C 0x021C 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x006C 0x021C 0x03E8 0x16 0x1 +#define MX93_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 0x006C 0x021C 0x03BC 0x7 0x0 +#define MX93_PAD_GPIO_IO24__GPIO2_IO24 0x0070 0x0220 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0220 0x0460 0x1 0x0 +#define MX93_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x0070 0x0220 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO24__TPM3_CH3 0x0070 0x0220 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO24__JTAG_MUX_TDO 0x0070 0x0220 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO24__LPSPI6_PCS1 0x0070 0x0220 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 0x0070 0x0220 0x03C0 0x7 0x0 +#define MX93_PAD_GPIO_IO25__GPIO2_IO25 0x0074 0x0224 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0224 0x0464 0x1 0x0 +#define MX93_PAD_GPIO_IO25__CAN2_TX 0x0074 0x0224 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x0074 0x0224 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO25__TPM4_CH3 0x0074 0x0224 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0224 0x03D4 0x5 0x1 +#define MX93_PAD_GPIO_IO25__LPSPI7_PCS1 0x0074 0x0224 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 0x0074 0x0224 0x03C4 0x7 0x0 +#define MX93_PAD_GPIO_IO26__GPIO2_IO26 0x0078 0x0228 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x0228 0x0468 0x1 0x0 +#define MX93_PAD_GPIO_IO26__PDM_BIT_STREAM01 0x0078 0x0228 0x043C 0x2 0x1 +#define MX93_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x0078 0x0228 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO26__TPM5_CH3 0x0078 0x0228 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x0228 0x03D8 0x5 0x1 +#define MX93_PAD_GPIO_IO26__LPSPI8_PCS1 0x0078 0x0228 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x0078 0x0228 0x0000 0x7 0x0 +#define MX93_PAD_GPIO_IO27__GPIO2_IO27 0x007C 0x022C 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO27__USDHC3_DATA3 0x007C 0x022C 0x046C 0x1 0x0 +#define MX93_PAD_GPIO_IO27__CAN2_RX 0x007C 0x022C 0x0364 0x2 0x1 +#define MX93_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x007C 0x022C 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO27__TPM6_CH3 0x007C 0x022C 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007C 0x022C 0x03DC 0x5 0x1 +#define MX93_PAD_GPIO_IO27__LPSPI5_PCS1 0x007C 0x022C 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 0x007C 0x022C 0x03C8 0x7 0x0 +#define MX93_PAD_GPIO_IO28__GPIO2_IO28 0x0080 0x0230 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0230 0x03E4 0x11 0x1 +#define MX93_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 0x0080 0x0230 0x0000 0x7 0x0 +#define MX93_PAD_GPIO_IO29__GPIO2_IO29 0x0084 0x0234 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0234 0x03E0 0x11 0x1 +#define MX93_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 0x0084 0x0234 0x0000 0x7 0x0 +#define MX93_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 0x0088 0x0238 0x0000 0x0 0x0 +#define MX93_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 0x0088 0x0238 0x0000 0x4 0x0 +#define MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x0088 0x0238 0x0000 0x5 0x0 +#define MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x008C 0x023C 0x0000 0x5 0x0 +#define MX93_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 0x008C 0x023C 0x0000 0x0 0x0 +#define MX93_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 0x008C 0x023C 0x03C8 0x4 0x1 +#define MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x0090 0x0240 0x0000 0x0 0x0 +#define MX93_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 0x0090 0x0240 0x0000 0x4 0x0 +#define MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x0090 0x0240 0x0000 0x5 0x0 +#define MX93_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 0x0094 0x0244 0x0000 0x0 0x0 +#define MX93_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 0x0094 0x0244 0x0000 0x4 0x0 +#define MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x0094 0x0244 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x0098 0x0248 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_MDC__LPUART3_DCB_B 0x0098 0x0248 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_MDC__I3C2_SCL 0x0098 0x0248 0x03CC 0x2 0x0 +#define MX93_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 0x0098 0x0248 0x0000 0x3 0x0 +#define MX93_PAD_ENET1_MDC__FLEXIO2_FLEXIO00 0x0098 0x0248 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_MDC__GPIO4_IO00 0x0098 0x0248 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x009C 0x024C 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_MDIO__LPUART3_RIN_B 0x009C 0x024C 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_MDIO__I3C2_SDA 0x009C 0x024C 0x03D0 0x2 0x0 +#define MX93_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 0x009C 0x024C 0x0000 0x3 0x0 +#define MX93_PAD_ENET1_MDIO__FLEXIO2_FLEXIO01 0x009C 0x024C 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x009C 0x024C 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x00A0 0x0250 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_TD3__CAN2_TX 0x00A0 0x0250 0x0000 0x2 0x0 +#define MX93_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 0x00A0 0x0250 0x0000 0x3 0x0 +#define MX93_PAD_ENET1_TD3__FLEXIO2_FLEXIO02 0x00A0 0x0250 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_TD3__GPIO4_IO02 0x00A0 0x0250 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x00A4 0x0254 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x00A4 0x0254 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_TD2__CAN2_RX 0x00A4 0x0254 0x0364 0x2 0x2 +#define MX93_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 0x00A4 0x0254 0x0000 0x3 0x0 +#define MX93_PAD_ENET1_TD2__FLEXIO2_FLEXIO03 0x00A4 0x0254 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_TD2__GPIO4_IO03 0x00A4 0x0254 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x00A8 0x0258 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_TD1__LPUART3_RTS_B 0x00A8 0x0258 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_TD1__I3C2_PUR 0x00A8 0x0258 0x0000 0x2 0x0 +#define MX93_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 0x00A8 0x0258 0x0000 0x3 0x0 +#define MX93_PAD_ENET1_TD1__FLEXIO2_FLEXIO04 0x00A8 0x0258 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_TD1__GPIO4_IO04 0x00A8 0x0258 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_TD1__I3C2_PUR_B 0x00A8 0x0258 0x0000 0x6 0x0 +#define MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x00AC 0x025C 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_TD0__LPUART3_TX 0x00AC 0x025C 0x041C 0x1 0x1 +#define MX93_PAD_ENET1_TD0__FLEXIO2_FLEXIO05 0x00AC 0x025C 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_TD0__GPIO4_IO05 0x00AC 0x025C 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x00B0 0x0260 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x00B0 0x0260 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO06 0x00B0 0x0260 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x00B0 0x0260 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x00B4 0x0264 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_TXC__ENET_QOS_TX_ER 0x00B4 0x0264 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_TXC__FLEXIO2_FLEXIO07 0x00B4 0x0264 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_TXC__GPIO4_IO07 0x00B4 0x0264 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x00B8 0x0268 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x00B8 0x0268 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 0x00B8 0x0268 0x0000 0x3 0x0 +#define MX93_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO08 0x00B8 0x0268 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x00B8 0x0268 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x00BC 0x026C 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x00BC 0x026C 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_RXC__FLEXIO2_FLEXIO09 0x00BC 0x026C 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_RXC__GPIO4_IO09 0x00BC 0x026C 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x00C0 0x0270 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_RD0__LPUART3_RX 0x00C0 0x0270 0x0418 0x1 0x1 +#define MX93_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 0x00C0 0x0270 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_RD0__GPIO4_IO10 0x00C0 0x0270 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x00C4 0x0274 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_RD1__LPUART3_CTS_B 0x00C4 0x0274 0x0414 0x1 0x1 +#define MX93_PAD_ENET1_RD1__LPTMR2_ALT1 0x00C4 0x0274 0x0408 0x3 0x0 +#define MX93_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 0x00C4 0x0274 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_RD1__GPIO4_IO11 0x00C4 0x0274 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x00C8 0x0278 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_RD2__LPTMR2_ALT2 0x00C8 0x0278 0x040C 0x3 0x0 +#define MX93_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 0x00C8 0x0278 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_RD2__GPIO4_IO12 0x00C8 0x0278 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x00CC 0x027C 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER 0x00CC 0x027C 0x0000 0x2 0x0 +#define MX93_PAD_ENET1_RD3__LPTMR2_ALT3 0x00CC 0x027C 0x0410 0x3 0x0 +#define MX93_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 0x00CC 0x027C 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_RD3__GPIO4_IO13 0x00CC 0x027C 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_MDC__ENET1_MDC 0x00D0 0x0280 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_MDC__LPUART4_DCB_B 0x00D0 0x0280 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_MDC__SAI2_RX_SYNC 0x00D0 0x0280 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 0x00D0 0x0280 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_MDC__GPIO4_IO14 0x00D0 0x0280 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x00D4 0x0284 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_MDIO__LPUART4_RIN_B 0x00D4 0x0284 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_MDIO__SAI2_RX_BCLK 0x00D4 0x0284 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 0x00D4 0x0284 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x00D4 0x0284 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_TD3__SAI2_RX_DATA00 0x00D8 0x0288 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 0x00D8 0x0288 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_TD3__GPIO4_IO16 0x00D8 0x0288 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x00D8 0x0288 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x00DC 0x028C 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x00DC 0x028C 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_TD2__SAI2_RX_DATA01 0x00DC 0x028C 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 0x00DC 0x028C 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_TD2__GPIO4_IO17 0x00DC 0x028C 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x00E0 0x0290 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_TD1__LPUART4_RTS_B 0x00E0 0x0290 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_TD1__SAI2_RX_DATA02 0x00E0 0x0290 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 0x00E0 0x0290 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_TD1__GPIO4_IO18 0x00E0 0x0290 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x00E4 0x0294 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_TD0__LPUART4_TX 0x00E4 0x0294 0x0428 0x1 0x1 +#define MX93_PAD_ENET2_TD0__SAI2_RX_DATA03 0x00E4 0x0294 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 0x00E4 0x0294 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_TD0__GPIO4_IO19 0x00E4 0x0294 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x00E8 0x0298 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x00E8 0x0298 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_TX_CTL__SAI2_TX_SYNC 0x00E8 0x0298 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 0x00E8 0x0298 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x00E8 0x0298 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x00EC 0x029C 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_TXC__ENET1_TX_ER 0x00EC 0x029C 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_TXC__SAI2_TX_BCLK 0x00EC 0x029C 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 0x00EC 0x029C 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_TXC__GPIO4_IO21 0x00EC 0x029C 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x00F0 0x02A0 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x00F0 0x02A0 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_RX_CTL__SAI2_TX_DATA00 0x00F0 0x02A0 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 0x00F0 0x02A0 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x00F0 0x02A0 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x00F4 0x02A4 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_RXC__ENET1_RX_ER 0x00F4 0x02A4 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_RXC__SAI2_TX_DATA01 0x00F4 0x02A4 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 0x00F4 0x02A4 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_RXC__GPIO4_IO23 0x00F4 0x02A4 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x00F8 0x02A8 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_RD0__LPUART4_RX 0x00F8 0x02A8 0x0424 0x1 0x1 +#define MX93_PAD_ENET2_RD0__SAI2_TX_DATA02 0x00F8 0x02A8 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 0x00F8 0x02A8 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_RD0__GPIO4_IO24 0x00F8 0x02A8 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x00FC 0x02AC 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_RD1__SPDIF_IN 0x00FC 0x02AC 0x0454 0x1 0x1 +#define MX93_PAD_ENET2_RD1__SAI2_TX_DATA03 0x00FC 0x02AC 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 0x00FC 0x02AC 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_RD1__GPIO4_IO25 0x00FC 0x02AC 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x0100 0x02B0 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_RD2__LPUART4_CTS_B 0x0100 0x02B0 0x0420 0x1 0x1 +#define MX93_PAD_ENET2_RD2__SAI2_MCLK 0x0100 0x02B0 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_RD2__MQS2_RIGHT 0x0100 0x02B0 0x0000 0x3 0x0 +#define MX93_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 0x0100 0x02B0 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_RD2__GPIO4_IO26 0x0100 0x02B0 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x0104 0x02B4 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_RD3__SPDIF_OUT 0x0104 0x02B4 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_RD3__SPDIF_IN 0x0104 0x02B4 0x0454 0x2 0x2 +#define MX93_PAD_ENET2_RD3__MQS2_LEFT 0x0104 0x02B4 0x0000 0x3 0x0 +#define MX93_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 0x0104 0x02B4 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_RD3__GPIO4_IO27 0x0104 0x02B4 0x0000 0x5 0x0 +#define MX93_PAD_SD1_CLK__FLEXIO1_FLEXIO08 0x0108 0x02B8 0x038C 0x4 0x1 +#define MX93_PAD_SD1_CLK__GPIO3_IO08 0x0108 0x02B8 0x0000 0x5 0x0 +#define MX93_PAD_SD1_CLK__USDHC1_CLK 0x0108 0x02B8 0x0000 0x0 0x0 +#define MX93_PAD_SD1_CMD__USDHC1_CMD 0x010C 0x02BC 0x0000 0x0 0x0 +#define MX93_PAD_SD1_CMD__FLEXIO1_FLEXIO09 0x010C 0x02BC 0x0390 0x4 0x1 +#define MX93_PAD_SD1_CMD__GPIO3_IO09 0x010C 0x02BC 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x0110 0x02C0 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 0x0110 0x02C0 0x0394 0x4 0x1 +#define MX93_PAD_SD1_DATA0__GPIO3_IO10 0x0110 0x02C0 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x0114 0x02C4 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 0x0114 0x02C4 0x0398 0x4 0x1 +#define MX93_PAD_SD1_DATA1__GPIO3_IO11 0x0114 0x02C4 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT 0x0114 0x02C4 0x0000 0x6 0x0 +#define MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x0118 0x02C8 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 0x0118 0x02C8 0x0000 0x4 0x0 +#define MX93_PAD_SD1_DATA2__GPIO3_IO12 0x0118 0x02C8 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY 0x0118 0x02C8 0x0000 0x6 0x0 +#define MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x011C 0x02CC 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x011C 0x02CC 0x0000 0x1 0x0 +#define MX93_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 0x011C 0x02CC 0x039C 0x4 0x1 +#define MX93_PAD_SD1_DATA3__GPIO3_IO13 0x011C 0x02CC 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x0120 0x02D0 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA4__FLEXSPI1_A_DATA04 0x0120 0x02D0 0x0000 0x1 0x0 +#define MX93_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 0x0120 0x02D0 0x03A0 0x4 0x1 +#define MX93_PAD_SD1_DATA4__GPIO3_IO14 0x0120 0x02D0 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x0124 0x02D4 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA5__FLEXSPI1_A_DATA05 0x0124 0x02D4 0x0000 0x1 0x0 +#define MX93_PAD_SD1_DATA5__USDHC1_RESET_B 0x0124 0x02D4 0x0000 0x2 0x0 +#define MX93_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 0x0124 0x02D4 0x03A4 0x4 0x1 +#define MX93_PAD_SD1_DATA5__GPIO3_IO15 0x0124 0x02D4 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x0128 0x02D8 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA6__FLEXSPI1_A_DATA06 0x0128 0x02D8 0x0000 0x1 0x0 +#define MX93_PAD_SD1_DATA6__USDHC1_CD_B 0x0128 0x02D8 0x0000 0x2 0x0 +#define MX93_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 0x0128 0x02D8 0x03A8 0x4 0x1 +#define MX93_PAD_SD1_DATA6__GPIO3_IO16 0x0128 0x02D8 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x012C 0x02DC 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA7__FLEXSPI1_A_DATA07 0x012C 0x02DC 0x0000 0x1 0x0 +#define MX93_PAD_SD1_DATA7__USDHC1_WP 0x012C 0x02DC 0x0000 0x2 0x0 +#define MX93_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 0x012C 0x02DC 0x03AC 0x4 0x1 +#define MX93_PAD_SD1_DATA7__GPIO3_IO17 0x012C 0x02DC 0x0000 0x5 0x0 +#define MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x0130 0x02E0 0x0000 0x0 0x0 +#define MX93_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x0130 0x02E0 0x0000 0x1 0x0 +#define MX93_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 0x0130 0x02E0 0x03B0 0x4 0x1 +#define MX93_PAD_SD1_STROBE__GPIO3_IO18 0x0130 0x02E0 0x0000 0x5 0x0 +#define MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x0134 0x02E4 0x0000 0x0 0x0 +#define MX93_PAD_SD2_VSELECT__USDHC2_WP 0x0134 0x02E4 0x0000 0x1 0x0 +#define MX93_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0134 0x02E4 0x0410 0x2 0x1 +#define MX93_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 0x0134 0x02E4 0x0000 0x4 0x0 +#define MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x0134 0x02E4 0x0000 0x5 0x0 +#define MX93_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 0x0134 0x02E4 0x0368 0x6 0x0 +#define MX93_PAD_SD3_CLK__USDHC3_CLK 0x0138 0x02E8 0x0458 0x0 0x1 +#define MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x0138 0x02E8 0x0000 0x1 0x0 +#define MX93_PAD_SD3_CLK__FLEXIO1_FLEXIO20 0x0138 0x02E8 0x03B4 0x4 0x1 +#define MX93_PAD_SD3_CLK__GPIO3_IO20 0x0138 0x02E8 0x0000 0x5 0x0 +#define MX93_PAD_SD3_CMD__USDHC3_CMD 0x013C 0x02EC 0x045C 0x0 0x1 +#define MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x013C 0x02EC 0x0000 0x1 0x0 +#define MX93_PAD_SD3_CMD__FLEXIO1_FLEXIO21 0x013C 0x02EC 0x0000 0x4 0x0 +#define MX93_PAD_SD3_CMD__GPIO3_IO21 0x013C 0x02EC 0x0000 0x5 0x0 +#define MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x0140 0x02F0 0x0460 0x0 0x1 +#define MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x0140 0x02F0 0x0000 0x1 0x0 +#define MX93_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 0x0140 0x02F0 0x03B8 0x4 0x1 +#define MX93_PAD_SD3_DATA0__GPIO3_IO22 0x0140 0x02F0 0x0000 0x5 0x0 +#define MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x0144 0x02F4 0x0464 0x0 0x1 +#define MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x0144 0x02F4 0x0000 0x1 0x0 +#define MX93_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 0x0144 0x02F4 0x03BC 0x4 0x1 +#define MX93_PAD_SD3_DATA1__GPIO3_IO23 0x0144 0x02F4 0x0000 0x5 0x0 +#define MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x0148 0x02F8 0x0468 0x0 0x1 +#define MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x0148 0x02F8 0x0000 0x1 0x0 +#define MX93_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 0x0148 0x02F8 0x03C0 0x4 0x1 +#define MX93_PAD_SD3_DATA2__GPIO3_IO24 0x0148 0x02F8 0x0000 0x5 0x0 +#define MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x014C 0x02FC 0x046C 0x0 0x1 +#define MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x014C 0x02FC 0x0000 0x1 0x0 +#define MX93_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 0x014C 0x02FC 0x03C4 0x4 0x1 +#define MX93_PAD_SD3_DATA3__GPIO3_IO25 0x014C 0x02FC 0x0000 0x5 0x0 +#define MX93_PAD_SD2_CD_B__USDHC2_CD_B 0x0150 0x0300 0x0000 0x0 0x0 +#define MX93_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN 0x0150 0x0300 0x0000 0x1 0x0 +#define MX93_PAD_SD2_CD_B__I3C2_SCL 0x0150 0x0300 0x03CC 0x2 0x1 +#define MX93_PAD_SD2_CD_B__FLEXIO1_FLEXIO00 0x0150 0x0300 0x036C 0x4 0x1 +#define MX93_PAD_SD2_CD_B__GPIO3_IO00 0x0150 0x0300 0x0000 0x5 0x0 +#define MX93_PAD_SD2_CLK__USDHC2_CLK 0x0154 0x0304 0x0000 0x0 0x0 +#define MX93_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT 0x0154 0x0304 0x0000 0x1 0x0 +#define MX93_PAD_SD2_CLK__I3C2_SDA 0x0154 0x0304 0x03D0 0x2 0x1 +#define MX93_PAD_SD2_CLK__FLEXIO1_FLEXIO01 0x0154 0x0304 0x0370 0x4 0x1 +#define MX93_PAD_SD2_CLK__GPIO3_IO01 0x0154 0x0304 0x0000 0x5 0x0 +#define MX93_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0154 0x0304 0x0000 0x6 0x0 +#define MX93_PAD_SD2_CMD__USDHC2_CMD 0x0158 0x0308 0x0000 0x0 0x0 +#define MX93_PAD_SD2_CMD__ENET1_1588_EVENT0_IN 0x0158 0x0308 0x0000 0x1 0x0 +#define MX93_PAD_SD2_CMD__I3C2_PUR 0x0158 0x0308 0x0000 0x2 0x0 +#define MX93_PAD_SD2_CMD__I3C2_PUR_B 0x0158 0x0308 0x0000 0x3 0x0 +#define MX93_PAD_SD2_CMD__FLEXIO1_FLEXIO02 0x0158 0x0308 0x0374 0x4 0x1 +#define MX93_PAD_SD2_CMD__GPIO3_IO02 0x0158 0x0308 0x0000 0x5 0x0 +#define MX93_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x0158 0x0308 0x0000 0x6 0x0 +#define MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x015C 0x030C 0x0000 0x0 0x0 +#define MX93_PAD_SD2_DATA0__ENET1_1588_EVENT0_OUT 0x015C 0x030C 0x0000 0x1 0x0 +#define MX93_PAD_SD2_DATA0__CAN2_TX 0x015C 0x030C 0x0000 0x2 0x0 +#define MX93_PAD_SD2_DATA0__FLEXIO1_FLEXIO03 0x015C 0x030C 0x0378 0x4 0x1 +#define MX93_PAD_SD2_DATA0__GPIO3_IO03 0x015C 0x030C 0x0000 0x5 0x0 +#define MX93_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x015C 0x030C 0x0000 0x6 0x0 +#define MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x0160 0x0310 0x0000 0x0 0x0 +#define MX93_PAD_SD2_DATA1__ENET1_1588_EVENT1_IN 0x0160 0x0310 0x0000 0x1 0x0 +#define MX93_PAD_SD2_DATA1__CAN2_RX 0x0160 0x0310 0x0364 0x2 0x3 +#define MX93_PAD_SD2_DATA1__FLEXIO1_FLEXIO04 0x0160 0x0310 0x037C 0x4 0x1 +#define MX93_PAD_SD2_DATA1__GPIO3_IO04 0x0160 0x0310 0x0000 0x5 0x0 +#define MX93_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x0160 0x0310 0x0000 0x6 0x0 +#define MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x0164 0x0314 0x0000 0x0 0x0 +#define MX93_PAD_SD2_DATA2__ENET1_1588_EVENT1_OUT 0x0164 0x0314 0x0000 0x1 0x0 +#define MX93_PAD_SD2_DATA2__MQS2_RIGHT 0x0164 0x0314 0x0000 0x2 0x0 +#define MX93_PAD_SD2_DATA2__FLEXIO1_FLEXIO05 0x0164 0x0314 0x0380 0x4 0x1 +#define MX93_PAD_SD2_DATA2__GPIO3_IO05 0x0164 0x0314 0x0000 0x5 0x0 +#define MX93_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0164 0x0314 0x0000 0x6 0x0 +#define MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x0168 0x0318 0x0000 0x0 0x0 +#define MX93_PAD_SD2_DATA3__LPTMR2_ALT1 0x0168 0x0318 0x0408 0x1 0x1 +#define MX93_PAD_SD2_DATA3__MQS2_LEFT 0x0168 0x0318 0x0000 0x2 0x0 +#define MX93_PAD_SD2_DATA3__FLEXIO1_FLEXIO06 0x0168 0x0318 0x0384 0x4 0x1 +#define MX93_PAD_SD2_DATA3__GPIO3_IO06 0x0168 0x0318 0x0000 0x5 0x0 +#define MX93_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0168 0x0318 0x0000 0x6 0x0 +#define MX93_PAD_SD2_RESET_B__USDHC2_RESET_B 0x016C 0x031C 0x0000 0x0 0x0 +#define MX93_PAD_SD2_RESET_B__LPTMR2_ALT2 0x016C 0x031C 0x040C 0x1 0x1 +#define MX93_PAD_SD2_RESET_B__FLEXIO1_FLEXIO07 0x016C 0x031C 0x0388 0x4 0x1 +#define MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x016C 0x031C 0x0000 0x5 0x0 +#define MX93_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x016C 0x031C 0x0000 0x6 0x0 +#define MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x0170 0x0320 0x0000 0x10 0x0 +#define MX93_PAD_I2C1_SCL__I3C1_SCL 0x0170 0x0320 0x0000 0x1 0x0 +#define MX93_PAD_I2C1_SCL__LPUART1_DCB_B 0x0170 0x0320 0x0000 0x2 0x0 +#define MX93_PAD_I2C1_SCL__TPM2_CH0 0x0170 0x0320 0x0000 0x3 0x0 +#define MX93_PAD_I2C1_SCL__GPIO1_IO00 0x0170 0x0320 0x0000 0x5 0x0 +#define MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x0174 0x0324 0x0000 0x10 0x0 +#define MX93_PAD_I2C1_SDA__I3C1_SDA 0x0174 0x0324 0x0000 0x1 0x0 +#define MX93_PAD_I2C1_SDA__LPUART1_RIN_B 0x0174 0x0324 0x0000 0x2 0x0 +#define MX93_PAD_I2C1_SDA__TPM2_CH1 0x0174 0x0324 0x0000 0x3 0x0 +#define MX93_PAD_I2C1_SDA__GPIO1_IO01 0x0174 0x0324 0x0000 0x5 0x0 +#define MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x0178 0x0328 0x0000 0x10 0x0 +#define MX93_PAD_I2C2_SCL__I3C1_PUR 0x0178 0x0328 0x0000 0x1 0x0 +#define MX93_PAD_I2C2_SCL__LPUART2_DCB_B 0x0178 0x0328 0x0000 0x2 0x0 +#define MX93_PAD_I2C2_SCL__TPM2_CH2 0x0178 0x0328 0x0000 0x3 0x0 +#define MX93_PAD_I2C2_SCL__SAI1_RX_SYNC 0x0178 0x0328 0x0000 0x4 0x0 +#define MX93_PAD_I2C2_SCL__GPIO1_IO02 0x0178 0x0328 0x0000 0x5 0x0 +#define MX93_PAD_I2C2_SCL__I3C1_PUR_B 0x0178 0x0328 0x0000 0x6 0x0 +#define MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x017C 0x032C 0x0000 0x10 0x0 +#define MX93_PAD_I2C2_SDA__LPUART2_RIN_B 0x017C 0x032C 0x0000 0x2 0x0 +#define MX93_PAD_I2C2_SDA__TPM2_CH3 0x017C 0x032C 0x0000 0x3 0x0 +#define MX93_PAD_I2C2_SDA__SAI1_RX_BCLK 0x017C 0x032C 0x0000 0x4 0x0 +#define MX93_PAD_I2C2_SDA__GPIO1_IO03 0x017C 0x032C 0x0000 0x5 0x0 +#define MX93_PAD_UART1_RXD__LPUART1_RX 0x0180 0x0330 0x0000 0x0 0x0 +#define MX93_PAD_UART1_RXD__S400_UART_RX 0x0180 0x0330 0x0000 0x1 0x0 +#define MX93_PAD_UART1_RXD__LPSPI2_SIN 0x0180 0x0330 0x0000 0x2 0x0 +#define MX93_PAD_UART1_RXD__TPM1_CH0 0x0180 0x0330 0x0000 0x3 0x0 +#define MX93_PAD_UART1_RXD__GPIO1_IO04 0x0180 0x0330 0x0000 0x5 0x0 +#define MX93_PAD_UART1_TXD__LPUART1_TX 0x0184 0x0334 0x0000 0x0 0x0 +#define MX93_PAD_UART1_TXD__S400_UART_TX 0x0184 0x0334 0x0000 0x1 0x0 +#define MX93_PAD_UART1_TXD__LPSPI2_PCS0 0x0184 0x0334 0x0000 0x2 0x0 +#define MX93_PAD_UART1_TXD__TPM1_CH1 0x0184 0x0334 0x0000 0x3 0x0 +#define MX93_PAD_UART1_TXD__GPIO1_IO05 0x0184 0x0334 0x0000 0x5 0x0 +#define MX93_PAD_UART2_RXD__LPUART2_RX 0x0188 0x0338 0x0000 0x0 0x0 +#define MX93_PAD_UART2_RXD__LPUART1_CTS_B 0x0188 0x0338 0x0000 0x1 0x0 +#define MX93_PAD_UART2_RXD__LPSPI2_SOUT 0x0188 0x0338 0x0000 0x2 0x0 +#define MX93_PAD_UART2_RXD__TPM1_CH2 0x0188 0x0338 0x0000 0x3 0x0 +#define MX93_PAD_UART2_RXD__SAI1_MCLK 0x0188 0x0338 0x0448 0x4 0x0 +#define MX93_PAD_UART2_RXD__GPIO1_IO06 0x0188 0x0338 0x0000 0x5 0x0 +#define MX93_PAD_UART2_TXD__LPUART2_TX 0x018C 0x033C 0x0000 0x0 0x0 +#define MX93_PAD_UART2_TXD__LPUART1_RTS_B 0x018C 0x033C 0x0000 0x1 0x0 +#define MX93_PAD_UART2_TXD__LPSPI2_SCK 0x018C 0x033C 0x0000 0x2 0x0 +#define MX93_PAD_UART2_TXD__TPM1_CH3 0x018C 0x033C 0x0000 0x3 0x0 +#define MX93_PAD_UART2_TXD__GPIO1_IO07 0x018C 0x033C 0x0000 0x5 0x0 +#define MX93_PAD_PDM_CLK__PDM_CLK 0x0190 0x0340 0x0000 0x0 0x0 +#define MX93_PAD_PDM_CLK__MQS1_LEFT 0x0190 0x0340 0x0000 0x1 0x0 +#define MX93_PAD_PDM_CLK__LPTMR1_ALT1 0x0190 0x0340 0x0000 0x4 0x0 +#define MX93_PAD_PDM_CLK__GPIO1_IO08 0x0190 0x0340 0x0000 0x5 0x0 +#define MX93_PAD_PDM_CLK__CAN1_TX 0x0190 0x0340 0x0000 0x6 0x0 +#define MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x0194 0x0344 0x0438 0x0 0x2 +#define MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x0194 0x0344 0x0000 0x1 0x0 +#define MX93_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x0194 0x0344 0x0000 0x2 0x0 +#define MX93_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x0194 0x0344 0x0000 0x3 0x0 +#define MX93_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x0194 0x0344 0x0000 0x4 0x0 +#define MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09 0x0194 0x0344 0x0000 0x5 0x0 +#define MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x0194 0x0344 0x0360 0x6 0x0 +#define MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x0198 0x0348 0x043C 0x0 0x2 +#define MX93_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI 0x0198 0x0348 0x0000 0x1 0x0 +#define MX93_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x0198 0x0348 0x0000 0x2 0x0 +#define MX93_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x0198 0x0348 0x0000 0x3 0x0 +#define MX93_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 0x0198 0x0348 0x0000 0x4 0x0 +#define MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x0198 0x0348 0x0000 0x5 0x0 +#define MX93_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 0x0198 0x0348 0x0368 0x6 0x1 +#define MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x019C 0x034C 0x0000 0x0 0x0 +#define MX93_PAD_SAI1_TXFS__SAI1_TX_DATA01 0x019C 0x034C 0x0000 0x1 0x0 +#define MX93_PAD_SAI1_TXFS__LPSPI1_PCS0 0x019C 0x034C 0x0000 0x2 0x0 +#define MX93_PAD_SAI1_TXFS__LPUART2_DTR_B 0x019C 0x034C 0x0000 0x3 0x0 +#define MX93_PAD_SAI1_TXFS__MQS1_LEFT 0x019C 0x034C 0x0000 0x4 0x0 +#define MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x019C 0x034C 0x0000 0x5 0x0 +#define MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x01A0 0x0350 0x0000 0x0 0x0 +#define MX93_PAD_SAI1_TXC__LPUART2_CTS_B 0x01A0 0x0350 0x0000 0x1 0x0 +#define MX93_PAD_SAI1_TXC__LPSPI1_SIN 0x01A0 0x0350 0x0000 0x2 0x0 +#define MX93_PAD_SAI1_TXC__LPUART1_DSR_B 0x01A0 0x0350 0x0000 0x3 0x0 +#define MX93_PAD_SAI1_TXC__CAN1_RX 0x01A0 0x0350 0x0360 0x4 0x1 +#define MX93_PAD_SAI1_TXC__GPIO1_IO12 0x01A0 0x0350 0x0000 0x5 0x0 +#define MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x01A4 0x0354 0x0000 0x0 0x0 +#define MX93_PAD_SAI1_TXD0__LPUART2_RTS_B 0x01A4 0x0354 0x0000 0x1 0x0 +#define MX93_PAD_SAI1_TXD0__LPSPI1_SCK 0x01A4 0x0354 0x0000 0x2 0x0 +#define MX93_PAD_SAI1_TXD0__LPUART1_DTR_B 0x01A4 0x0354 0x0000 0x3 0x0 +#define MX93_PAD_SAI1_TXD0__CAN1_TX 0x01A4 0x0354 0x0000 0x4 0x0 +#define MX93_PAD_SAI1_TXD0__GPIO1_IO13 0x01A4 0x0354 0x0000 0x5 0x0 +#define MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x01A8 0x0358 0x0000 0x0 0x0 +#define MX93_PAD_SAI1_RXD0__SAI1_MCLK 0x01A8 0x0358 0x0448 0x1 0x1 +#define MX93_PAD_SAI1_RXD0__LPSPI1_SOUT 0x01A8 0x0358 0x0000 0x2 0x0 +#define MX93_PAD_SAI1_RXD0__LPUART2_DSR_B 0x01A8 0x0358 0x0000 0x3 0x0 +#define MX93_PAD_SAI1_RXD0__MQS1_RIGHT 0x01A8 0x0358 0x0000 0x4 0x0 +#define MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x01A8 0x0358 0x0000 0x5 0x0 +#define MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x01AC 0x035C 0x0000 0x0 0x0 +#define MX93_PAD_WDOG_ANY__GPIO1_IO15 0x01AC 0x035C 0x0000 0x5 0x0 + +#endif /* __DTS_IMX93_PINFUNC_H */ diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi new file mode 100644 index 000000000000..f83a07c7c9b1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -0,0 +1,334 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include <dt-bindings/clock/imx93-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +#include "imx93-pinfunc.h" + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + serial5 = &lpuart6; + serial6 = &lpuart7; + serial7 = &lpuart8; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A55_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A55_1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + }; + + osc_32k: clock-osc-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "osc_32k"; + }; + + osc_24m: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + clk_ext1: clock-ext1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext1"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <24000000>; + arm,no-tick-in-suspend; + interrupt-parent = <&gic>; + }; + + gic: interrupt-controller@48000000 { + compatible = "arm,gic-v3"; + reg = <0 0x48000000 0 0x10000>, + <0 0x48040000 0 0xc0000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x80000000>, + <0x28000000 0x0 0x28000000 0x10000000>; + + aips1: bus@44000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x44000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mu1: mailbox@44230000 { + compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; + reg = <0x44230000 0x10000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + status = "disabled"; + }; + + system_counter: timer@44290000 { + compatible = "nxp,sysctr-timer"; + reg = <0x44290000 0x30000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc_24m>; + clock-names = "per"; + }; + + lpuart1: serial@44380000 { + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x44380000 0x1000>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART1_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart2: serial@44390000 { + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x44390000 0x1000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART2_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + + iomuxc: pinctrl@443c0000 { + compatible = "fsl,imx93-iomuxc"; + reg = <0x443c0000 0x10000>; + status = "okay"; + }; + + clk: clock-controller@44450000 { + compatible = "fsl,imx93-ccm"; + reg = <0x44450000 0x10000>; + #clock-cells = <1>; + clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>; + clock-names = "osc_32k", "osc_24m", "clk_ext1"; + status = "okay"; + }; + + anatop: anatop@44480000 { + compatible = "fsl,imx93-anatop", "syscon"; + reg = <0x44480000 0x10000>; + }; + }; + + aips2: bus@42000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x42000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mu2: mailbox@42440000 { + compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; + reg = <0x42440000 0x10000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + status = "disabled"; + }; + + lpuart3: serial@42570000 { + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x42570000 0x1000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART3_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart4: serial@42580000 { + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x42580000 0x1000>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART4_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart5: serial@42590000 { + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x42590000 0x1000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART5_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart6: serial@425a0000 { + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x425a0000 0x1000>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART6_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart7: serial@42690000 { + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x42690000 0x1000>; + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART7_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart8: serial@426a0000 { + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x426a0000 0x1000>; + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART8_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + }; + + aips3: bus@42800000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x42800000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usdhc1: mmc@42850000 { + compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42850000 0x10000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_USDHC1_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc2: mmc@42860000 { + compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42860000 0x10000>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_USDHC2_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc3: mmc@428b0000 { + compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x428b0000 0x10000>; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_USDHC3_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + }; + + gpio2: gpio@43810080 { + compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; + reg = <0x43810080 0x1000>, <0x43810040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 32 32>; + }; + + gpio3: gpio@43820080 { + compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; + reg = <0x43820080 0x1000>, <0x43820040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 64 32>; + }; + + gpio4: gpio@43830080 { + compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; + reg = <0x43830080 0x1000>, <0x43830040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 96 32>; + }; + + gpio1: gpio@47400080 { + compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; + reg = <0x47400080 0x1000>, <0x47400040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 0 32>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/mba8mx.dtsi b/arch/arm64/boot/dts/freescale/mba8mx.dtsi index c2f0f1a1566c..104bdd4e437a 100644 --- a/arch/arm64/boot/dts/freescale/mba8mx.dtsi +++ b/arch/arm64/boot/dts/freescale/mba8mx.dtsi @@ -16,7 +16,6 @@ }; chosen { - // bootargs = "console=ttymxc2,115200 earlycon=ec_imx6q,0x30880000,115200"; stdout-path = &uart3; }; @@ -26,21 +25,21 @@ pinctrl-0 = <&pinctrl_gpiobutton>; autorepeat; - switch1 { + switch-1 { label = "switch1"; linux,code = <BTN_0>; gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; wakeup-source; }; - btn2: switch2 { + btn2: switch-2 { label = "switch2"; linux,code = <BTN_1>; gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; wakeup-source; }; - switch3 { + switch-3 { label = "switch3"; linux,code = <BTN_2>; gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; @@ -272,7 +271,6 @@ status = "okay"; }; -/* UART4 is assigned to Cortex-M4 */ &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; |