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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-10-17 19:55:56 +0300 |
|---|---|---|
| committer | Marc Zyngier <marc.zyngier@arm.com> | 2017-10-19 13:22:39 +0300 |
| commit | 558b01654d92332d3b7b17bf773cdce8ce16ef46 (patch) | |
| tree | 52c1a98cbd4cc0e950801328a92404ce6db85b50 /arch/arm64/Kconfig | |
| parent | 9d111d49106b61f5a652d5418e85d8741b1a0427 (diff) | |
| download | linux-558b01654d92332d3b7b17bf773cdce8ce16ef46.tar.xz | |
irqchip/gic-v3: Add workaround for Synquacer pre-ITS
The Socionext Synquacer SoC's implementation of GICv3 has a so-called
'pre-ITS', which maps 32-bit writes targeted at a separate window of
size '4 << device_id_bits' onto writes to GITS_TRANSLATER with device
ID taken from bits [device_id_bits + 1:2] of the window offset.
Writes that target GITS_TRANSLATER directly are reported as originating
from device ID #0.
So add a workaround for this. Given that this breaks isolation, clear
the IRQ_DOMAIN_FLAG_MSI_REMAP flag as well.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'arch/arm64/Kconfig')
| -rw-r--r-- | arch/arm64/Kconfig | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 0df64a6a56d4..c4361dff2b74 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -539,6 +539,14 @@ config QCOM_QDF2400_ERRATUM_0065 If unsure, say Y. +config SOCIONEXT_SYNQUACER_PREITS + bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" + default y + help + Socionext Synquacer SoCs implement a separate h/w block to generate + MSI doorbell writes with non-zero values for the device ID. + + If unsure, say Y. endmenu |