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| author | Paul Walmsley <paul@pwsan.com> | 2009-06-20 05:08:26 +0400 |
|---|---|---|
| committer | paul <paul@twilight.(none)> | 2009-06-20 05:09:31 +0400 |
| commit | c9812d042a21eb492a36cfabf9f41107f5ecee3d (patch) | |
| tree | f9443de1d4534b0b56bd1b0ff56bfc6d78eb698d /arch/arm/plat-omap/include/mach/sram.h | |
| parent | 2f135eaf182761bb9a5cbd5138a447b0ad2a1fef (diff) | |
| download | linux-c9812d042a21eb492a36cfabf9f41107f5ecee3d.tar.xz | |
OMAP3 clock: add a short delay when lowering CORE clk rate
When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2
divider, add a short delay before returning to SDRAM to allow the SDRC
time to stabilize. Without this delay, the system is prone to random
panics upon re-entering SDRAM.
This time delay varies based on MPU frequency. At 500MHz MPU frequency at
room temperature, 64 loops seems to work okay; so add another 32 loops for
environmental and process variation.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/plat-omap/include/mach/sram.h')
| -rw-r--r-- | arch/arm/plat-omap/include/mach/sram.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h index dca7c16ae903..c32fa0a220dc 100644 --- a/arch/arm/plat-omap/include/mach/sram.h +++ b/arch/arm/plat-omap/include/mach/sram.h @@ -24,7 +24,7 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, u32 m2, - u32 unlock_dll); + u32 unlock_dll, u32 f); /* Do not use these */ extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); @@ -62,7 +62,7 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz; extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, u32 m2, - u32 unlock_dll); + u32 unlock_dll, u32 f); extern unsigned long omap3_sram_configure_core_dpll_sz; #endif |