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| author | Joseph Lo <josephl@nvidia.com> | 2012-11-13 06:04:48 +0400 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2012-11-16 02:09:22 +0400 |
| commit | 29a0e7beab8e05be53d5b9c050253a4dc417041e (patch) | |
| tree | eddaa429e909f209cb0628b0733e0ade8e277fd0 /arch/arm/mach-tegra/common.c | |
| parent | d552920a02759cdc45d8507868de10ac2f5b9a18 (diff) | |
| download | linux-29a0e7beab8e05be53d5b9c050253a4dc417041e.tar.xz | |
ARM: tegra: retain L2 content over CPU suspend/resume
The L2 RAM is in different power domain from the CPU cluster. So the
L2 content can be retained over CPU suspend/resume. To do that, we
need to disable L2 after the MMU is disabled, and enable L2 before
the MMU is enabled. But the L2 controller is in the same power domain
with the CPU cluster. We need to restore it's settings and re-enable
it after the power be resumed.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/common.c')
| -rw-r--r-- | arch/arm/mach-tegra/common.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 203a8b94863b..11a74db51e5d 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -36,6 +36,7 @@ #include "pmc.h" #include "apbio.h" #include "sleep.h" +#include "pm.h" /* * Storage for debug-macro.S's state. @@ -117,6 +118,7 @@ static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = { static void __init tegra_init_cache(void) { #ifdef CONFIG_CACHE_L2X0 + int ret; void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; u32 aux_ctrl, cache_type; @@ -124,7 +126,9 @@ static void __init tegra_init_cache(void) aux_ctrl = (cache_type & 0x700) << (17-8); aux_ctrl |= 0x7C400001; - l2x0_of_init(aux_ctrl, 0x8200c3fe); + ret = l2x0_of_init(aux_ctrl, 0x8200c3fe); + if (!ret) + l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs); #endif } |