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| author | Ingo Molnar <mingo@elte.hu> | 2010-08-31 11:45:21 +0400 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2010-08-31 11:45:46 +0400 |
| commit | daab7fc734a53fdeaf844b7c03053118ad1769da (patch) | |
| tree | 575deb3cdcc6dda562acaed6f7c29bc81ae01cf2 /arch/arm/include/asm/cache.h | |
| parent | 774ea0bcb27f57b6fd521b3b6c43237782fed4b9 (diff) | |
| parent | 2bfc96a127bc1cc94d26bfaa40159966064f9c8c (diff) | |
| download | linux-daab7fc734a53fdeaf844b7c03053118ad1769da.tar.xz | |
Merge commit 'v2.6.36-rc3' into x86/memblock
Conflicts:
arch/x86/kernel/trampoline.c
mm/memblock.c
Merge reason: Resolve the conflicts, update to latest upstream.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/arm/include/asm/cache.h')
| -rw-r--r-- | arch/arm/include/asm/cache.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index 66c160b8547f..9d6122096fbe 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -14,7 +14,7 @@ * cache before the transfer is done, causing old data to be seen by * the CPU. */ -#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES +#define ARCH_DMA_MINALIGN L1_CACHE_BYTES /* * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers. |