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| author | Daniel Schultz <d.schultz@phytec.de> | 2018-02-13 12:44:32 +0300 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2018-02-15 12:13:09 +0300 |
| commit | 5ce0bad4ccd04c8a989e94d3c89e4e796ac22e48 (patch) | |
| tree | 0862d10fde72053127a72d9fcc4d22c304fcbb29 /arch/arm/boot/dts | |
| parent | 7928b2cbe55b2a410a0f5c1f154610059c57b1b2 (diff) | |
| download | linux-5ce0bad4ccd04c8a989e94d3c89e4e796ac22e48.tar.xz | |
ARM: dts: rockchip: Remove 1.8 GHz operation point from phycore som
Rockchip recommends to run the CPU cores only with operations points of
1.6 GHz or lower.
Removed the cpu0 node with too high operation points and use the default
values instead.
Fixes: 903d31e34628 ("ARM: dts: rockchip: Add support for phyCORE-RK3288 SoM")
Cc: stable@vger.kernel.org
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm/boot/dts')
| -rw-r--r-- | arch/arm/boot/dts/rk3288-phycore-som.dtsi | 20 |
1 files changed, 0 insertions, 20 deletions
diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rk3288-phycore-som.dtsi index 99cfae875e12..5eae4776ffde 100644 --- a/arch/arm/boot/dts/rk3288-phycore-som.dtsi +++ b/arch/arm/boot/dts/rk3288-phycore-som.dtsi @@ -110,26 +110,6 @@ }; }; -&cpu0 { - cpu0-supply = <&vdd_cpu>; - operating-points = < - /* KHz uV */ - 1800000 1400000 - 1608000 1350000 - 1512000 1300000 - 1416000 1200000 - 1200000 1100000 - 1008000 1050000 - 816000 1000000 - 696000 950000 - 600000 900000 - 408000 900000 - 312000 900000 - 216000 900000 - 126000 900000 - >; -}; - &emmc { status = "okay"; bus-width = <8>; |