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authorFlorian Fainelli <f.fainelli@gmail.com>2021-10-27 22:37:29 +0300
committerFlorian Fainelli <f.fainelli@gmail.com>2021-11-16 06:09:40 +0300
commit754c4050a00e802e122690112fc2c3a6abafa7e2 (patch)
tree8e37bf9aa0a3871e602b833d08107de70e9ff173 /arch/arm/boot/dts/tegra124-peripherals-opp.dtsi
parentfa55b7dcdc43c1aa1ba12bca9d2dd4318c2a0dbf (diff)
downloadlinux-754c4050a00e802e122690112fc2c3a6abafa7e2.tar.xz
ARM: dts: BCM5301X: Fix I2C controller interrupt
The I2C interrupt controller line is off by 32 because the datasheet describes interrupt inputs into the GIC which are for Shared Peripheral Interrupts and are starting at offset 32. The ARM GIC binding expects the SPI interrupts to be numbered from 0 relative to the SPI base. Fixes: bb097e3e0045 ("ARM: dts: BCM5301X: Add I2C support to the DT") Tested-by: Christian Lamparter <chunkeey@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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