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| author | Icenowy Zheng <icenowy@aosc.io> | 2020-09-23 03:58:53 +0300 |
|---|---|---|
| committer | Maxime Ripard <maxime@cerno.tech> | 2020-09-28 13:09:22 +0300 |
| commit | c0dcfbe29edcc90d90da6b84e7d45ef39e67a726 (patch) | |
| tree | aa99b0398a37f42099a95c3b70d0f6433a796778 /arch/arm/boot/dts/sun8i-v3s.dtsi | |
| parent | 02ed6bb83ec3f99806b0f3471c7ee1a02525e236 (diff) | |
| download | linux-c0dcfbe29edcc90d90da6b84e7d45ef39e67a726.tar.xz | |
ARM: dts: sun8i: V3/V3s/S3/S3L: add pinctrl for UART2 RX/TX
The UART2 RX/TX pins on Allwinner V3 series is at PB0/1, which is used
as debugging UART on some boards.
Add pinctrl node for them.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20200923005858.148261-1-icenowy@aosc.io
Diffstat (limited to 'arch/arm/boot/dts/sun8i-v3s.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/sun8i-v3s.dtsi | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 7d40897dab09..4cfdf193cf88 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -322,6 +322,11 @@ function = "uart0"; }; + uart2_pins: uart2-pins { + pins = "PB0", "PB1"; + function = "uart2"; + }; + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -397,6 +402,8 @@ reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART2>; resets = <&ccu RST_BUS_UART2>; + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; status = "disabled"; }; |