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authorMiquel Raynal <miquel.raynal@bootlin.com>2018-04-24 18:55:02 +0300
committerMaxime Ripard <maxime.ripard@bootlin.com>2018-04-25 10:02:55 +0300
commitbc3bd041fe766219a44688b182c260064007f0cc (patch)
tree69c47e0c3829ea64e75861395e6493090ad528ed /arch/arm/boot/dts/sun8i-a23-a33.dtsi
parent9a209c6e952c71b00ee29dbf6cab0da766be7fe0 (diff)
downloadlinux-bc3bd041fe766219a44688b182c260064007f0cc.tar.xz
ARM: dts: sun8i: a23/a33: declare NAND pins
Declare NAND pins (bus, chip select and ready/busy) for a23/a33 SoCs. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'arch/arm/boot/dts/sun8i-a23-a33.dtsi')
-rw-r--r--arch/arm/boot/dts/sun8i-a23-a33.dtsi33
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 971f9be699a7..44f3cad3de75 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -198,6 +198,8 @@
clock-names = "ahb", "mod";
resets = <&ccu RST_BUS_NAND>;
reset-names = "ahb";
+ pinctrl-names = "default";
+ pinctrl-0 = <&nand_pins &nand_pins_cs0 &nand_pins_rb0>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -315,6 +317,37 @@
bias-pull-up;
};
+ nand_pins: nand-pins {
+ pins = "PC0", "PC1", "PC2", "PC5",
+ "PC8", "PC9", "PC10", "PC11",
+ "PC12", "PC13", "PC14", "PC15";
+ function = "nand0";
+ };
+
+ nand_pins_cs0: nand-pins-cs0 {
+ pins = "PC4";
+ function = "nand0";
+ bias-pull-up;
+ };
+
+ nand_pins_cs1: nand-pins-cs1 {
+ pins = "PC3";
+ function = "nand0";
+ bias-pull-up;
+ };
+
+ nand_pins_rb0: nand-pins-rb0 {
+ pins = "PC6";
+ function = "nand0";
+ bias-pull-up;
+ };
+
+ nand_pins_rb1: nand-pins-rb1 {
+ pins = "PC7";
+ function = "nand0";
+ bias-pull-up;
+ };
+
pwm0_pins: pwm0 {
pins = "PH0";
function = "pwm0";