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authorMaxime Ripard <maxime.ripard@free-electrons.com>2017-02-01 11:53:23 +0300
committerMaxime Ripard <maxime.ripard@free-electrons.com>2017-02-02 13:50:50 +0300
commit9af684efc74e6a9ac56047461f3f424d03942d88 (patch)
tree4e9468f97a48cf6898aad1f3ba187e3e06ad8d64 /arch/arm/boot/dts/sun8i-a23-a33.dtsi
parent487a07fba0c9755864283c6c79d7ea86e811070a (diff)
downloadlinux-9af684efc74e6a9ac56047461f3f424d03942d88.tar.xz
ARM: sun8i: dt: Add mali node
The A23 and A33 have an ARM Mali 400 GPU. Now that we have a binding, add it to our DT. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun8i-a23-a33.dtsi')
-rw-r--r--arch/arm/boot/dts/sun8i-a23-a33.dtsi26
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index d92fdf5a7b26..35008b78d899 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -472,6 +472,32 @@
#size-cells = <0>;
};
+ mali: gpu@1c40000 {
+ compatible = "allwinner,sun8i-a23-mali",
+ "allwinner,sun7i-a20-mali", "arm,mali-400";
+ reg = <0x01c40000 0x10000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1",
+ "pmu";
+ clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
+ clock-names = "bus", "core";
+ resets = <&ccu RST_BUS_GPU>;
+
+ assigned-clocks = <&ccu CLK_GPU>;
+ assigned-clock-rates = <408000000>;
+ };
+
gic: interrupt-controller@01c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,