diff options
| author | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2023-12-05 18:33:17 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-01-24 17:56:27 +0300 |
| commit | 81924ec7a0d50f6fe3ed5a616ae3ef30f1edd932 (patch) | |
| tree | 7eb4e055a666cf829978e54ba08665a68a1e6d15 /arch/arm/boot/dts/qcom/qcom-msm8660.dtsi | |
| parent | ffb05e91b68bc58484b94b5d3d1aa8e559278fd6 (diff) | |
| download | linux-81924ec7a0d50f6fe3ed5a616ae3ef30f1edd932.tar.xz | |
ARM: dts: qcom: use defines for interrupts
Replace hard-coded interrupt parts (GIC, flags) with standard defines
for readability. No changes in resulting DTBs.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231205153317.346109-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/qcom/qcom-msm8660.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/qcom/qcom-msm8660.dtsi | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi index a7c245b9c8f9..17188fe54617 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi @@ -47,7 +47,7 @@ cpu-pmu { compatible = "qcom,scorpion-mp-pmu"; - interrupts = <1 9 0x304>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; }; clocks { @@ -89,9 +89,9 @@ timer@2000000 { compatible = "qcom,scss-timer", "qcom,msm-timer"; - interrupts = <1 0 0x301>, - <1 1 0x301>, - <1 2 0x301>; + interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; reg = <0x02000000 0x100>; clock-frequency = <27000000>, <32768>; @@ -105,7 +105,7 @@ gpio-controller; gpio-ranges = <&tlmm 0 0 173>; #gpio-cells = <2>; - interrupts = <0 16 0x4>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; @@ -283,7 +283,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x19c40000 0x1000>, <0x19c00000 0x1000>; - interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -292,7 +292,7 @@ gsbi12_i2c: i2c@19c80000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x19c80000 0x1000>; - interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>; clock-names = "core", "iface"; #address-cells = <1>; |