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authorOleksij Rempel <o.rempel@pengutronix.de>2023-01-31 11:46:30 +0300
committerShawn Guo <shawnguo@kernel.org>2023-03-06 05:01:46 +0300
commit5417c655b98ed385d18695a9fbb384883a0d1f47 (patch)
tree2b3c425b51daf462a9ec9e8f6a73302f545ac58d /arch/arm/boot/dts/imx6dl-plybas.dts
parentaad004c1382c186d1c787155f8ce8a5ee98a9974 (diff)
downloadlinux-5417c655b98ed385d18695a9fbb384883a0d1f47.tar.xz
ARM: dts: imx6dl-plybas: configure ethernet reference clock parent
On this board the PHY is the ref clock provider. So, configure ethernet reference clock as input. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6dl-plybas.dts')
-rw-r--r--arch/arm/boot/dts/imx6dl-plybas.dts12
1 files changed, 8 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/imx6dl-plybas.dts b/arch/arm/boot/dts/imx6dl-plybas.dts
index c52e6caf3996..e98046eea7a4 100644
--- a/arch/arm/boot/dts/imx6dl-plybas.dts
+++ b/arch/arm/boot/dts/imx6dl-plybas.dts
@@ -75,6 +75,7 @@
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
+ clock-output-names = "enet_ref_pad";
};
reg_5v0: regulator-5v0 {
@@ -99,6 +100,13 @@
status = "okay";
};
+&clks {
+ clocks = <&clk50m_phy>;
+ clock-names = "enet_ref_pad";
+ assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
+ assigned-clock-parents = <&clk50m_phy>;
+};
+
&ecspi1 {
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
@@ -116,10 +124,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rmii";
- clocks = <&clks IMX6QDL_CLK_ENET>,
- <&clks IMX6QDL_CLK_ENET>,
- <&clk50m_phy>;
- clock-names = "ipg", "ahb", "ptp";
phy-handle = <&rgmii_phy>;
status = "okay";