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| author | Franklin S Cooper Jr <fcooper@ti.com> | 2017-07-26 05:15:52 +0300 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2017-08-14 21:34:24 +0300 |
| commit | a46394beb0ea1cd7b8b4344c5af990ce711e8324 (patch) | |
| tree | cd35b85ac45d65da00a7a52509885fc88eef4a22 /arch/arm/boot/dts/dra7-evm.dts | |
| parent | 78b02c36e43cd34a9d830507929ae77b074e6d0a (diff) | |
| download | linux-a46394beb0ea1cd7b8b4344c5af990ce711e8324.tar.xz | |
ARM: dts: dra7xx: Enable NAND dma prefetch by default
Currently the default method of prefetch polled shows the highest
possible read and write speed when minimal non NAND background
activity is being done. But it is also very CPU intensive to reach
these high speeds (CPU load of 99% via mtd performance tests). While
DMA prefetch only uses 50% of the CPU to achieve around 23% less in
top read and write performance.
However, as the non NAND CPU load increases the read and write
performance takes a large hit when using polled prefetch. Therefore,
prefetch dma mode ends up outperforming prefetch polled in general
"system level" test. So switch to using dma prefetch by default since
it is likely what most users would prefer.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/dra7-evm.dts')
| -rw-r--r-- | arch/arm/boot/dts/dra7-evm.dts | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index 343872acdd29..ee04d8d7abab 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -564,6 +564,7 @@ interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ + ti,nand-xfer-type = "prefetch-dma"; ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <16>; |