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| author | Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> | 2017-01-26 23:09:38 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2017-01-31 23:03:56 +0300 |
| commit | a50477e55fff69e1028f25624ee9fc9182d59b1f (patch) | |
| tree | 7dd6af7e656b9e879f506f825dbb1e744fb59b7c /MAINTAINERS | |
| parent | 39d75485689de9abd2b27e9b2771c48db8e4be23 (diff) | |
| download | linux-a50477e55fff69e1028f25624ee9fc9182d59b1f.tar.xz | |
ASoC: Intel: cht_bsw_rt5645: add Baytrail MCLK support
The existing code assumes a 19.2 MHz MCLK as the default
hardware configuration. This is valid for CherryTrail but
not for Baytrail.
Add explicit MCLK configuration to set the 19.2 clock on/off
depending on DAPM events.
This is a prerequisite step to enable devices with Baytrail
and RT5645 such as Asus X205TA
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'MAINTAINERS')
0 files changed, 0 insertions, 0 deletions