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| author | Dmitry Osipenko <digetx@gmail.com> | 2018-04-09 22:28:25 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2018-04-27 12:14:35 +0300 |
| commit | 60eb8eff54f8b3ea388ee91b9ec652acb856fdf3 (patch) | |
| tree | b51b6fb7f2e89105c176d6f67deab307b6037628 /Documentation | |
| parent | ca545e6c803d54a2dbffe783eb08ab177b3c4f0d (diff) | |
| download | linux-60eb8eff54f8b3ea388ee91b9ec652acb856fdf3.tar.xz | |
dt-bindings: arm: tegra: Document #reset-cells property of the Tegra20 MC
Memory Controller has a memory client "hot reset" functionality, which
resets the DMA interface of a memory client, so MC is a reset controller.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt index f9632bacbd04..7d60a50a4fa1 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt @@ -6,11 +6,21 @@ Required properties: example below. Note that the MC registers are interleaved with the GART registers, and hence must be represented as multiple ranges. - interrupts : Should contain MC General interrupt. +- #reset-cells : Should be 1. This cell represents memory client module ID. + The assignments may be found in header file <dt-bindings/memory/tegra20-mc.h> + or in the TRM documentation. Example: - memory-controller@7000f000 { + mc: memory-controller@7000f000 { compatible = "nvidia,tegra20-mc"; reg = <0x7000f000 0x024 0x7000f03c 0x3c4>; interrupts = <0 77 0x04>; + #reset-cells = <1>; + }; + + video-codec@6001a000 { + compatible = "nvidia,tegra20-vde"; + ... + resets = <&mc TEGRA20_MC_RESET_VDE>; }; |